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6bfc6b8665
A vector add may be faster than a vector shift. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D106689
810 lines
38 KiB
TableGen
810 lines
38 KiB
TableGen
//===- RISCVInstrInfoVSDPatterns.td - RVV SDNode patterns --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This file contains the required infrastructure and SDNode patterns to
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/// support code generation for the standard 'V' (Vector) extension, version
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/// 0.10. This version is still experimental as the 'V' extension hasn't been
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/// ratified yet.
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///
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/// This file is included from and depends upon RISCVInstrInfoVPseudos.td
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///
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/// Note: the patterns for RVV intrinsics are found in
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/// RISCVInstrInfoVPseudos.td.
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Helpers to define the SDNode patterns.
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//===----------------------------------------------------------------------===//
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def SDTSplatI64 : SDTypeProfile<1, 1, [
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SDTCVecEltisVT<0, i64>, SDTCisVT<1, i32>
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]>;
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def rv32_splat_i64 : SDNode<"RISCVISD::SPLAT_VECTOR_I64", SDTSplatI64>;
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def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>,
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SDTCisVT<1, XLenVT>]>;
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def riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>;
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def riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>;
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def rvv_vnot : PatFrag<(ops node:$in),
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(xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>;
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// Give explicit Complexity to prefer simm5/uimm5.
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def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [splat_vector, rv32_splat_i64], [], 1>;
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def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [splat_vector, rv32_splat_i64], [], 2>;
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def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [splat_vector, rv32_splat_i64], [], 2>;
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def SplatPat_simm5_plus1
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: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1",
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[splat_vector, rv32_splat_i64], [], 2>;
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def SplatPat_simm5_plus1_nonzero
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: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero",
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[splat_vector, rv32_splat_i64], [], 2>;
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class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
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dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
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}
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multiclass VPatUSLoadStoreSDNode<ValueType type,
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int log2sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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VReg reg_class,
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int sew = !shl(1, log2sew)>
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{
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defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
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defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX);
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// Load
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def : Pat<(type (load BaseAddr:$rs1)),
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(load_instr BaseAddr:$rs1, avl, log2sew)>;
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// Store
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def : Pat<(store type:$rs2, BaseAddr:$rs1),
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(store_instr reg_class:$rs2, BaseAddr:$rs1, avl, log2sew)>;
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}
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multiclass VPatUSLoadStoreWholeVRSDNode<ValueType type,
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int log2sew,
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LMULInfo vlmul,
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VReg reg_class,
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int sew = !shl(1, log2sew)>
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{
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defvar load_instr =
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!cast<Instruction>("VL"#!substr(vlmul.MX, 1)#"RE"#sew#"_V");
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defvar store_instr =
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!cast<Instruction>("VS"#!substr(vlmul.MX, 1)#"R_V");
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// Load
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def : Pat<(type (load BaseAddr:$rs1)),
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(load_instr BaseAddr:$rs1)>;
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// Store
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def : Pat<(store type:$rs2, BaseAddr:$rs1),
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(store_instr reg_class:$rs2, BaseAddr:$rs1)>;
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}
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multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m>
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{
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defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#m.BX);
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defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#m.BX);
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// Load
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def : Pat<(m.Mask (load BaseAddr:$rs1)),
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(load_instr BaseAddr:$rs1, m.AVL, m.Log2SEW)>;
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// Store
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def : Pat<(store m.Mask:$rs2, BaseAddr:$rs1),
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(store_instr VR:$rs2, BaseAddr:$rs1, m.AVL, m.Log2SEW)>;
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}
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class VPatBinarySDNode_VV<SDNode vop,
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string instruction_name,
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ValueType result_type,
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ValueType op_type,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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VReg RetClass,
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VReg op_reg_class> :
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Pat<(result_type (vop
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(op_type op_reg_class:$rs1),
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(op_type op_reg_class:$rs2))),
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(!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX)
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op_reg_class:$rs1,
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op_reg_class:$rs2,
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avl, sew)>;
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class VPatBinarySDNode_XI<SDNode vop,
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string instruction_name,
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string suffix,
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ValueType result_type,
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ValueType vop_type,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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VReg RetClass,
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VReg vop_reg_class,
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ComplexPattern SplatPatKind,
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DAGOperand xop_kind> :
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Pat<(result_type (vop
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(vop_type vop_reg_class:$rs1),
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(vop_type (SplatPatKind xop_kind:$rs2)))),
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(!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX)
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vop_reg_class:$rs1,
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xop_kind:$rs2,
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avl, sew)>;
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multiclass VPatBinarySDNode_VV_VX<SDNode vop, string instruction_name> {
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foreach vti = AllIntegerVectors in {
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def : VPatBinarySDNode_VV<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
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def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
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vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
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SplatPat, GPR>;
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}
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}
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multiclass VPatBinarySDNode_VV_VX_VI<SDNode vop, string instruction_name,
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Operand ImmType = simm5>
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: VPatBinarySDNode_VV_VX<vop, instruction_name> {
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foreach vti = AllIntegerVectors in {
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def : VPatBinarySDNode_XI<vop, instruction_name, "VI",
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vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
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!cast<ComplexPattern>(SplatPat#_#ImmType),
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ImmType>;
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}
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}
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class VPatBinarySDNode_VF<SDNode vop,
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string instruction_name,
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ValueType result_type,
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ValueType vop_type,
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ValueType xop_type,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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VReg RetClass,
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VReg vop_reg_class,
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DAGOperand xop_kind> :
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Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
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(vop_type (splat_vector xop_kind:$rs2)))),
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(!cast<Instruction>(instruction_name#"_"#vlmul.MX)
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vop_reg_class:$rs1,
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(xop_type xop_kind:$rs2),
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avl, sew)>;
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multiclass VPatBinaryFPSDNode_VV_VF<SDNode vop, string instruction_name> {
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foreach vti = AllFloatVectors in {
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def : VPatBinarySDNode_VV<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
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def : VPatBinarySDNode_VF<vop, instruction_name#"_V"#vti.ScalarSuffix,
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vti.Vector, vti.Vector, vti.Scalar, vti.Mask,
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vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
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vti.ScalarRegClass>;
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}
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}
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multiclass VPatBinaryFPSDNode_R_VF<SDNode vop, string instruction_name> {
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foreach fvti = AllFloatVectors in
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def : Pat<(fvti.Vector (vop (fvti.Vector (splat_vector fvti.Scalar:$rs2)),
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(fvti.Vector fvti.RegClass:$rs1))),
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(!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
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fvti.RegClass:$rs1,
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(fvti.Scalar fvti.ScalarRegClass:$rs2),
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fvti.AVL, fvti.Log2SEW)>;
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}
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multiclass VPatIntegerSetCCSDNode_VV<CondCode cc,
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string instruction_name,
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bit swap = 0> {
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foreach vti = AllIntegerVectors in {
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defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX);
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def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
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(vti.Vector vti.RegClass:$rs2), cc)),
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SwapHelper<(instruction),
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(instruction vti.RegClass:$rs1),
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(instruction vti.RegClass:$rs2),
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(instruction vti.AVL, vti.Log2SEW),
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swap>.Value>;
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}
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}
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multiclass VPatIntegerSetCCSDNode_XI<CondCode cc,
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string instruction_name,
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string kind,
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ComplexPattern SplatPatKind,
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DAGOperand xop_kind,
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bit swap = 0> {
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foreach vti = AllIntegerVectors in {
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defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
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def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
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(vti.Vector (SplatPatKind xop_kind:$rs2)), cc)),
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SwapHelper<(instruction),
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(instruction vti.RegClass:$rs1),
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(instruction xop_kind:$rs2),
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(instruction vti.AVL, vti.Log2SEW),
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swap>.Value>;
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}
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}
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multiclass VPatIntegerSetCCSDNode_VV_VX_VI<CondCode cc,
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string instruction_name,
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bit swap = 0> {
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defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
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defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
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SplatPat, GPR, swap>;
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defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
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SplatPat_simm5, simm5, swap>;
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}
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multiclass VPatIntegerSetCCSDNode_VV_VX<CondCode cc,
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string instruction_name,
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bit swap = 0> {
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defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
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defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
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SplatPat, GPR, swap>;
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}
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multiclass VPatIntegerSetCCSDNode_VX_VI<CondCode cc,
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string instruction_name,
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bit swap = 0> {
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defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
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SplatPat, GPR, swap>;
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defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
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SplatPat_simm5, simm5, swap>;
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}
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multiclass VPatIntegerSetCCSDNode_VIPlus1<CondCode cc, string instruction_name,
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ComplexPattern splatpat_kind> {
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foreach vti = AllIntegerVectors in {
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defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
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def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
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(vti.Vector (splatpat_kind simm5:$rs2)),
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cc)),
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(instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
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vti.AVL, vti.Log2SEW)>;
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}
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}
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multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc,
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string inst_name,
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string swapped_op_inst_name> {
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foreach fvti = AllFloatVectors in {
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def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Vector fvti.RegClass:$rs2),
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cc)),
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(!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, fvti.RegClass:$rs2, fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1),
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(splat_vector fvti.ScalarRegClass:$rs2),
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cc)),
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(!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Mask (setcc (splat_vector fvti.ScalarRegClass:$rs2),
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(fvti.Vector fvti.RegClass:$rs1),
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cc)),
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(!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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}
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}
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multiclass VPatExtendSDNode_V<list<SDNode> ops, string inst_name, string suffix,
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list <VTypeInfoToFraction> fraction_list> {
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foreach vtiTofti = fraction_list in {
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defvar vti = vtiTofti.Vti;
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defvar fti = vtiTofti.Fti;
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foreach op = ops in
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def : Pat<(vti.Vector (op (fti.Vector fti.RegClass:$rs2))),
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(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX)
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fti.RegClass:$rs2, fti.AVL, vti.Log2SEW)>;
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}
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}
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multiclass VPatConvertI2FPSDNode_V<SDNode vop, string instruction_name> {
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foreach fvti = AllFloatVectors in {
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defvar ivti = GetIntVTypeInfo<fvti>.Vti;
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def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
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ivti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
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}
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}
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multiclass VPatConvertFP2ISDNode_V<SDNode vop, string instruction_name> {
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foreach fvti = AllFloatVectors in {
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defvar ivti = GetIntVTypeInfo<fvti>.Vti;
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def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))),
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(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
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fvti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW)>;
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}
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}
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multiclass VPatWConvertI2FPSDNode_V<SDNode vop, string instruction_name> {
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foreach vtiToWti = AllWidenableIntToFloatVectors in {
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defvar ivti = vtiToWti.Vti;
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defvar fwti = vtiToWti.Wti;
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def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
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(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
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ivti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW)>;
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}
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}
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multiclass VPatWConvertFP2ISDNode_V<SDNode vop, string instruction_name> {
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foreach fvtiToFWti = AllWidenableFloatVectors in {
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defvar fvti = fvtiToFWti.Vti;
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defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
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def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
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}
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}
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multiclass VPatNConvertI2FPSDNode_V<SDNode vop, string instruction_name> {
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foreach fvtiToFWti = AllWidenableFloatVectors in {
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defvar fvti = fvtiToFWti.Vti;
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defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
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def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1))),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
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iwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
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}
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}
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multiclass VPatNConvertFP2ISDNode_V<SDNode vop, string instruction_name> {
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foreach vtiToWti = AllWidenableIntToFloatVectors in {
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defvar vti = vtiToWti.Vti;
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defvar fwti = vtiToWti.Wti;
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def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1))),
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(!cast<Instruction>(instruction_name#"_"#vti.LMul.MX)
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fwti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Patterns.
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtV] in {
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// 7.4. Vector Unit-Stride Instructions
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foreach vti = !listconcat(FractionalGroupIntegerVectors,
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FractionalGroupFloatVectors) in
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defm : VPatUSLoadStoreSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
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vti.AVL, vti.RegClass>;
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foreach vti = [VI8M1, VI16M1, VI32M1, VI64M1, VF16M1, VF32M1, VF64M1] in
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defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
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vti.RegClass>;
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foreach vti = !listconcat(GroupIntegerVectors, GroupFloatVectors) in
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defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
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vti.RegClass>;
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foreach mti = AllMasks in
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defm : VPatUSLoadStoreMaskSDNode<mti>;
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// 12.1. Vector Single-Width Integer Add and Subtract
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defm : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;
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defm : VPatBinarySDNode_VV_VX<sub, "PseudoVSUB">;
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// Handle VRSUB specially since it's the only integer binary op with reversed
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// pattern operands
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foreach vti = AllIntegerVectors in {
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def : Pat<(sub (vti.Vector (SplatPat GPR:$rs2)),
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(vti.Vector vti.RegClass:$rs1)),
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(!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX)
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vti.RegClass:$rs1, GPR:$rs2, vti.AVL, vti.Log2SEW)>;
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def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)),
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(vti.Vector vti.RegClass:$rs1)),
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(!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX)
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vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>;
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}
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// 12.3. Vector Integer Extension
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defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF2",
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AllFractionableVF2IntVectors>;
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defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF2",
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AllFractionableVF2IntVectors>;
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defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4",
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AllFractionableVF4IntVectors>;
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defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4",
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AllFractionableVF4IntVectors>;
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defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF8",
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AllFractionableVF8IntVectors>;
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defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF8",
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AllFractionableVF8IntVectors>;
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// 12.5. Vector Bitwise Logical Instructions
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defm : VPatBinarySDNode_VV_VX_VI<and, "PseudoVAND">;
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defm : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">;
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defm : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">;
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// 12.6. Vector Single-Width Bit Shift Instructions
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defm : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
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defm : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
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defm : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
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foreach vti = AllIntegerVectors in {
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// Emit shift by 1 as an add since it might be faster.
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def : Pat<(shl (vti.Vector vti.RegClass:$rs1),
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(vti.Vector (splat_vector (XLenVT 1)))),
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(!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
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vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
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}
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foreach vti = [VI64M1, VI64M2, VI64M4, VI64M8] in {
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def : Pat<(shl (vti.Vector vti.RegClass:$rs1),
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(vti.Vector (rv32_splat_i64 (XLenVT 1)))),
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(!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
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vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
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}
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// 12.8. Vector Integer Comparison Instructions
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defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ, "PseudoVMSEQ">;
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defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE, "PseudoVMSNE">;
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defm : VPatIntegerSetCCSDNode_VV_VX<SETLT, "PseudoVMSLT">;
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defm : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;
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defm : VPatIntegerSetCCSDNode_VIPlus1<SETLT, "PseudoVMSLE",
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SplatPat_simm5_plus1>;
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defm : VPatIntegerSetCCSDNode_VIPlus1<SETULT, "PseudoVMSLEU",
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SplatPat_simm5_plus1_nonzero>;
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defm : VPatIntegerSetCCSDNode_VV<SETGT, "PseudoVMSLT", /*swap*/1>;
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defm : VPatIntegerSetCCSDNode_VV<SETUGT, "PseudoVMSLTU", /*swap*/1>;
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defm : VPatIntegerSetCCSDNode_VX_VI<SETGT, "PseudoVMSGT">;
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defm : VPatIntegerSetCCSDNode_VX_VI<SETUGT, "PseudoVMSGTU">;
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defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETLE, "PseudoVMSLE">;
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defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETULE, "PseudoVMSLEU">;
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defm : VPatIntegerSetCCSDNode_VV<SETGE, "PseudoVMSLE", /*swap*/1>;
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defm : VPatIntegerSetCCSDNode_VV<SETUGE, "PseudoVMSLEU", /*swap*/1>;
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defm : VPatIntegerSetCCSDNode_VIPlus1<SETGE, "PseudoVMSGT",
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SplatPat_simm5_plus1>;
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defm : VPatIntegerSetCCSDNode_VIPlus1<SETUGE, "PseudoVMSGTU",
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SplatPat_simm5_plus1_nonzero>;
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// 12.9. Vector Integer Min/Max Instructions
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defm : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;
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defm : VPatBinarySDNode_VV_VX<smin, "PseudoVMIN">;
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defm : VPatBinarySDNode_VV_VX<umax, "PseudoVMAXU">;
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defm : VPatBinarySDNode_VV_VX<smax, "PseudoVMAX">;
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// 12.10. Vector Single-Width Integer Multiply Instructions
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defm : VPatBinarySDNode_VV_VX<mul, "PseudoVMUL">;
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defm : VPatBinarySDNode_VV_VX<mulhs, "PseudoVMULH">;
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defm : VPatBinarySDNode_VV_VX<mulhu, "PseudoVMULHU">;
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// 12.11. Vector Integer Divide Instructions
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defm : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU">;
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defm : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV">;
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defm : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU">;
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defm : VPatBinarySDNode_VV_VX<srem, "PseudoVREM">;
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// 12.13 Vector Single-Width Integer Multiply-Add Instructions.
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foreach vti = AllIntegerVectors in {
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// NOTE: We choose VMADD because it has the most commuting freedom. So it
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// works best with how TwoAddressInstructionPass tries commuting.
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defvar suffix = vti.LMul.MX # "_COMMUTABLE";
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def : Pat<(vti.Vector (add vti.RegClass:$rs2,
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(mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))),
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(!cast<Instruction>("PseudoVMADD_VV_"# suffix)
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vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
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vti.AVL, vti.Log2SEW)>;
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def : Pat<(vti.Vector (sub vti.RegClass:$rs2,
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(mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))),
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(!cast<Instruction>("PseudoVNMSUB_VV_"# suffix)
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vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
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vti.AVL, vti.Log2SEW)>;
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// The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally
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// commutable.
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def : Pat<(vti.Vector (add vti.RegClass:$rs2,
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(mul_oneuse (SplatPat XLenVT:$rs1),
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vti.RegClass:$rd))),
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(!cast<Instruction>("PseudoVMADD_VX_" # suffix)
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vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
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vti.AVL, vti.Log2SEW)>;
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def : Pat<(vti.Vector (sub vti.RegClass:$rs2,
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(mul_oneuse (SplatPat XLenVT:$rs1),
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vti.RegClass:$rd))),
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(!cast<Instruction>("PseudoVNMSUB_VX_" # suffix)
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vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
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vti.AVL, vti.Log2SEW)>;
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}
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// 12.15. Vector Integer Merge Instructions
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foreach vti = AllIntegerVectors in {
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def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), vti.RegClass:$rs1,
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vti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX)
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vti.RegClass:$rs2, vti.RegClass:$rs1, VMV0:$vm,
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vti.AVL, vti.Log2SEW)>;
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def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat XLenVT:$rs1),
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vti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX)
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vti.RegClass:$rs2, GPR:$rs1, VMV0:$vm, vti.AVL, vti.Log2SEW)>;
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def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat_simm5 simm5:$rs1),
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vti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX)
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vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, vti.AVL, vti.Log2SEW)>;
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}
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// 12.1. Vector Single-Width Saturating Add and Subtract
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defm : VPatBinarySDNode_VV_VX_VI<saddsat, "PseudoVSADD">;
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defm : VPatBinarySDNode_VV_VX_VI<uaddsat, "PseudoVSADDU">;
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defm : VPatBinarySDNode_VV_VX<ssubsat, "PseudoVSSUB">;
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defm : VPatBinarySDNode_VV_VX<usubsat, "PseudoVSSUBU">;
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// 16.1. Vector Mask-Register Logical Instructions
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foreach mti = AllMasks in {
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def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)),
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(!cast<Instruction>("PseudoVMAND_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
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def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)),
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(!cast<Instruction>("PseudoVMOR_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
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def : Pat<(mti.Mask (xor VR:$rs1, VR:$rs2)),
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(!cast<Instruction>("PseudoVMXOR_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
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def : Pat<(mti.Mask (rvv_vnot (and VR:$rs1, VR:$rs2))),
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(!cast<Instruction>("PseudoVMNAND_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
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def : Pat<(mti.Mask (rvv_vnot (or VR:$rs1, VR:$rs2))),
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(!cast<Instruction>("PseudoVMNOR_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
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def : Pat<(mti.Mask (rvv_vnot (xor VR:$rs1, VR:$rs2))),
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(!cast<Instruction>("PseudoVMXNOR_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
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def : Pat<(mti.Mask (and VR:$rs1, (rvv_vnot VR:$rs2))),
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(!cast<Instruction>("PseudoVMANDNOT_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
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def : Pat<(mti.Mask (or VR:$rs1, (rvv_vnot VR:$rs2))),
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(!cast<Instruction>("PseudoVMORNOT_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
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// Handle rvv_vnot the same as the vmnot.m pseudoinstruction.
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def : Pat<(mti.Mask (rvv_vnot VR:$rs)),
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(!cast<Instruction>("PseudoVMNAND_MM_"#mti.LMul.MX)
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VR:$rs, VR:$rs, mti.AVL, mti.Log2SEW)>;
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}
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} // Predicates = [HasStdExtV]
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let Predicates = [HasStdExtV, HasStdExtF] in {
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// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
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defm : VPatBinaryFPSDNode_VV_VF<fadd, "PseudoVFADD">;
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defm : VPatBinaryFPSDNode_VV_VF<fsub, "PseudoVFSUB">;
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defm : VPatBinaryFPSDNode_R_VF<fsub, "PseudoVFRSUB">;
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// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
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defm : VPatBinaryFPSDNode_VV_VF<fmul, "PseudoVFMUL">;
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defm : VPatBinaryFPSDNode_VV_VF<fdiv, "PseudoVFDIV">;
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defm : VPatBinaryFPSDNode_R_VF<fdiv, "PseudoVFRDIV">;
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// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions.
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foreach fvti = AllFloatVectors in {
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// NOTE: We choose VFMADD because it has the most commuting freedom. So it
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// works best with how TwoAddressInstructionPass tries commuting.
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defvar suffix = fvti.LMul.MX # "_COMMUTABLE";
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def : Pat<(fvti.Vector (fma fvti.RegClass:$rs1, fvti.RegClass:$rd,
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fvti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVFMADD_VV_"# suffix)
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fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (fma fvti.RegClass:$rs1, fvti.RegClass:$rd,
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(fneg fvti.RegClass:$rs2))),
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(!cast<Instruction>("PseudoVFMSUB_VV_"# suffix)
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fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd,
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(fneg fvti.RegClass:$rs2))),
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(!cast<Instruction>("PseudoVFNMADD_VV_"# suffix)
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fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd,
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fvti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix)
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fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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// The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally
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// commutable.
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def : Pat<(fvti.Vector (fma (splat_vector fvti.ScalarRegClass:$rs1),
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fvti.RegClass:$rd, fvti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVFMADD_V" # fvti.ScalarSuffix # "_" # suffix)
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fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (fma (splat_vector fvti.ScalarRegClass:$rs1),
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fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))),
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(!cast<Instruction>("PseudoVFMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
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fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (fma (splat_vector fvti.ScalarRegClass:$rs1),
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(fneg fvti.RegClass:$rd), (fneg fvti.RegClass:$rs2))),
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(!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix)
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fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (fma (splat_vector fvti.ScalarRegClass:$rs1),
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(fneg fvti.RegClass:$rd), fvti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
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fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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// The splat might be negated.
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def : Pat<(fvti.Vector (fma (fneg (splat_vector fvti.ScalarRegClass:$rs1)),
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fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))),
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(!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix)
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fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (fma (fneg (splat_vector fvti.ScalarRegClass:$rs1)),
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fvti.RegClass:$rd, fvti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
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fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
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fvti.AVL, fvti.Log2SEW)>;
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}
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foreach vti = AllFloatVectors in {
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// 14.8. Vector Floating-Point Square-Root Instruction
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def : Pat<(fsqrt (vti.Vector vti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX)
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vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>;
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// 14.12. Vector Floating-Point Sign-Injection Instructions
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def : Pat<(fabs (vti.Vector vti.RegClass:$rs)),
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(!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX)
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vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>;
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// Handle fneg with VFSGNJN using the same input for both operands.
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def : Pat<(fneg (vti.Vector vti.RegClass:$rs)),
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(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
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vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>;
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def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
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(vti.Vector vti.RegClass:$rs2))),
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(!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX)
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vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>;
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def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
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(vti.Vector (splat_vector vti.ScalarRegClass:$rs2)))),
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(!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
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vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW)>;
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def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
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(vti.Vector (fneg vti.RegClass:$rs2)))),
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(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
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vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>;
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def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
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(vti.Vector (fneg (splat_vector vti.ScalarRegClass:$rs2))))),
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(!cast<Instruction>("PseudoVFSGNJN_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
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vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW)>;
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}
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// 14.11. Vector Floating-Point MIN/MAX Instructions
|
|
defm : VPatBinaryFPSDNode_VV_VF<fminnum, "PseudoVFMIN">;
|
|
defm : VPatBinaryFPSDNode_VV_VF<fmaxnum, "PseudoVFMAX">;
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|
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// 14.13. Vector Floating-Point Compare Instructions
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defm : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
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defm : VPatFPSetCCSDNode_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
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defm : VPatFPSetCCSDNode_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">;
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defm : VPatFPSetCCSDNode_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">;
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defm : VPatFPSetCCSDNode_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
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defm : VPatFPSetCCSDNode_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">;
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defm : VPatFPSetCCSDNode_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">;
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defm : VPatFPSetCCSDNode_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">;
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// Floating-point vselects:
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// 12.15. Vector Integer Merge Instructions
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// 14.15. Vector Floating-Point Merge Instruction
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foreach fvti = AllFloatVectors in {
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def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), fvti.RegClass:$rs1,
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fvti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX)
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fvti.RegClass:$rs2, fvti.RegClass:$rs1, VMV0:$vm,
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fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
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(splat_vector fvti.ScalarRegClass:$rs1),
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fvti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX)
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fvti.RegClass:$rs2,
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(fvti.Scalar fvti.ScalarRegClass:$rs1),
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VMV0:$vm, fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
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(splat_vector (fvti.Scalar fpimm0)),
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fvti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)
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fvti.RegClass:$rs2, 0, VMV0:$vm, fvti.AVL, fvti.Log2SEW)>;
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}
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// 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
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defm : VPatConvertFP2ISDNode_V<fp_to_sint, "PseudoVFCVT_RTZ_X_F_V">;
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defm : VPatConvertFP2ISDNode_V<fp_to_uint, "PseudoVFCVT_RTZ_XU_F_V">;
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defm : VPatConvertI2FPSDNode_V<sint_to_fp, "PseudoVFCVT_F_X_V">;
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defm : VPatConvertI2FPSDNode_V<uint_to_fp, "PseudoVFCVT_F_XU_V">;
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// 14.18. Widening Floating-Point/Integer Type-Convert Instructions
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defm : VPatWConvertFP2ISDNode_V<fp_to_sint, "PseudoVFWCVT_RTZ_X_F_V">;
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defm : VPatWConvertFP2ISDNode_V<fp_to_uint, "PseudoVFWCVT_RTZ_XU_F_V">;
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defm : VPatWConvertI2FPSDNode_V<sint_to_fp, "PseudoVFWCVT_F_X_V">;
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defm : VPatWConvertI2FPSDNode_V<uint_to_fp, "PseudoVFWCVT_F_XU_V">;
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foreach fvtiToFWti = AllWidenableFloatVectors in {
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defvar fvti = fvtiToFWti.Vti;
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defvar fwti = fvtiToFWti.Wti;
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def : Pat<(fwti.Vector (fpextend (fvti.Vector fvti.RegClass:$rs1))),
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(!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
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}
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// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
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defm : VPatNConvertFP2ISDNode_V<fp_to_sint, "PseudoVFNCVT_RTZ_X_F_W">;
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defm : VPatNConvertFP2ISDNode_V<fp_to_uint, "PseudoVFNCVT_RTZ_XU_F_W">;
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defm : VPatNConvertI2FPSDNode_V<sint_to_fp, "PseudoVFNCVT_F_X_W">;
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defm : VPatNConvertI2FPSDNode_V<uint_to_fp, "PseudoVFNCVT_F_XU_W">;
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foreach fvtiToFWti = AllWidenableFloatVectors in {
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defvar fvti = fvtiToFWti.Vti;
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defvar fwti = fvtiToFWti.Wti;
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def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
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(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX)
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fwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
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}
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} // Predicates = [HasStdExtV, HasStdExtF]
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//===----------------------------------------------------------------------===//
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// Vector Splats
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtV] in {
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foreach vti = AllIntegerVectors in {
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def : Pat<(vti.Vector (SplatPat GPR:$rs1)),
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(!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
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GPR:$rs1, vti.AVL, vti.Log2SEW)>;
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def : Pat<(vti.Vector (SplatPat_simm5 simm5:$rs1)),
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(!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
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simm5:$rs1, vti.AVL, vti.Log2SEW)>;
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}
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} // Predicates = [HasStdExtV]
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let Predicates = [HasStdExtV, HasStdExtF] in {
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foreach fvti = AllFloatVectors in {
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def : Pat<(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs1)),
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(!cast<Instruction>("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
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(fvti.Scalar fvti.ScalarRegClass:$rs1),
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fvti.AVL, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (splat_vector (fvti.Scalar fpimm0))),
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(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
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0, fvti.AVL, fvti.Log2SEW)>;
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}
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} // Predicates = [HasStdExtV, HasStdExtF]
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//===----------------------------------------------------------------------===//
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// Vector Element Extracts
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//===----------------------------------------------------------------------===//
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|
let Predicates = [HasStdExtV, HasStdExtF] in
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foreach vti = AllFloatVectors in {
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|
defvar vmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_",
|
|
vti.ScalarSuffix,
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|
"_S_", vti.LMul.MX));
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// Only pattern-match extract-element operations where the index is 0. Any
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// other index will have been custom-lowered to slide the vector correctly
|
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// into place.
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def : Pat<(vti.Scalar (extractelt (vti.Vector vti.RegClass:$rs2), 0)),
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(vmv_f_s_inst vti.RegClass:$rs2, vti.Log2SEW)>;
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}
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