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llvm-mirror/test/CodeGen/MIR
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David Stuttard bbae73ce2c [AMDGPU] Add support for immediate operand for S_ENDPGM 
Summary:
Add support for immediate operand in S_ENDPGM

Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6

Reviewers: alexshap

Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59213

llvm-svn: 355902
2019-03-12 09:52:58 +00:00
..
AArch64
MIR: Validate LLT types when parsing
2019-02-04 22:59:56 +00:00
AMDGPU
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
ARM
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
Generic
[codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL
2018-10-01 21:59:45 +00:00
Hexagon
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
Mips
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
NVPTX
[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.
2018-01-10 00:56:48 +00:00
PowerPC
[Power9] Allow gpr callee saved spills in prologue to vectors registers
2018-11-09 16:36:24 +00:00
WebAssembly
[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)
2018-05-08 02:02:50 +00:00
X86
[X86] Add FPCW as an implicit use on floating point load instructions.
2019-02-08 20:50:09 +00:00
README
Add README describing the intention of test/CodeGen/MIR
2016-12-09 20:16:12 +00:00

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.