David Green 9b21f6c6fa [ARM] Add MVE addressing to isLegalT2AddressImmediate ... Now with MVE being added, we can add the vector addressing mode costs for it. These are generally imm7 multiplied by the size of the type being loaded / stored. Differential Revision: https://reviews.llvm.org/D62967 llvm-svn: 362873		2019-06-08 10:18:23 +00:00
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AArch64
AMDGPU	TTI: Improve default costs for addrspacecast	2019-06-03 18:41:34 +00:00
ARM	[ARM] Add MVE addressing to isLegalT2AddressImmediate	2019-06-08 10:18:23 +00:00
PowerPC	Revert "[llvm] r359313 - [PowerPC] Update P9 vector costs for insert/extract element"	2019-05-01 05:01:03 +00:00
RISCV	[RISCV] Disable test/Analysis/CostModel/RISCV tests if RISCV backend not built	2019-06-06 10:12:28 +00:00
SystemZ	[CodeMetrics] Don't let extends of i1 be free.	2019-05-17 01:26:35 +00:00
X86	[CostModel][X86] Improve masked load/store AVX1/AVX2 costs	2019-06-02 20:37:02 +00:00
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