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81a9bfe915
This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> llvm-svn: 292982
39 lines
1.7 KiB
LLVM
39 lines
1.7 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s
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; CHECK-LABEL: {{^}}test1:
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; CHECK: image_store
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0){{$}}
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; CHECK-NEXT: image_store
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <4 x float> %d0, <4 x float> %d1, i32 %c0, i32 %c1) {
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call void @llvm.amdgcn.image.store.v4f32.i32.v8i32(<4 x float> %d0, i32 %c0, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 1, i1 0)
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call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00
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call void @llvm.amdgcn.image.store.v4f32.i32.v8i32(<4 x float> %d1, i32 %c1, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 1, i1 0)
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ret void
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}
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; Test that the intrinsic is merged with automatically generated waits and
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; emitted as late as possible.
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;
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; CHECK-LABEL: {{^}}test2:
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; CHECK: image_load
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: s_waitcnt
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; CHECK-NEXT: image_store
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define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, i32 %c) {
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%t = call <4 x float> @llvm.amdgcn.image.load.v4f32.i32.v8i32(i32 %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00
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%c.1 = mul i32 %c, 2
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call void @llvm.amdgcn.image.store.v4f32.i32.v8i32(<4 x float> %t, i32 %c.1, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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ret void
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}
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declare void @llvm.amdgcn.s.waitcnt(i32) #0
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declare <4 x float> @llvm.amdgcn.image.load.v4f32.i32.v8i32(i32, <8 x i32>, i32, i1, i1, i1, i1) #1
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declare void @llvm.amdgcn.image.store.v4f32.i32.v8i32(<4 x float>, i32, <8 x i32>, i32, i1, i1, i1, i1) #0
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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