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9b23d4365f
llvm-mirror/test/CodeGen
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Stanislav Mekhanoshin 9b23d4365f [AMDGPU] Combine DS operations with offsets bigger than byte 
In many cases ds operations can be combined even if offsets do not
fit into 8 bit encoding. What it takes is to adjust base address.

Differential Revision: https://reviews.llvm.org/D31993

llvm-svn: 300227
2017-04-13 17:53:07 +00:00
..
AArch64 [GlobalISel] LegalizerInfo: Enable legalization of non-power-of-2 types 2017-04-11 10:10:14 +00:00
AMDGPU [AMDGPU] Combine DS operations with offsets bigger than byte 2017-04-13 17:53:07 +00:00
ARM GlobalISel: Allow legalizing G_FADD to a libcall 2017-04-11 10:52:34 +00:00
AVR
BPF Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
Generic [Hexagon] Unxfail passing tests 2017-04-13 16:05:35 +00:00
Hexagon Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
Inputs
Lanai
Mips Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
MIR MIR: Allow parsing of empty machine functions 2017-04-11 19:32:41 +00:00
MSP430
NVPTX Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
PowerPC [PowerPC] multiply-with-overflow might use the CTR register 2017-04-11 02:03:17 +00:00
SPARC
SystemZ Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
Thumb Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
Thumb2 Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
WebAssembly
WinEH
X86 [GlobalIsel][X86] support G_CONSTANT selection. 2017-04-12 12:54:54 +00:00
XCore