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The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
48 lines
1.4 KiB
LLVM
48 lines
1.4 KiB
LLVM
; Test some complicated looping constructs to ensure that they
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; compile successfully and that some sort of branching is used
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; in the resulting code.
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;
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; RUN: llc < %s -march=mblaze -mattr=+mul,+fpu,+barrel | FileCheck %s
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declare i32 @printf(i8*, ...)
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@MSG = internal constant [19 x i8] c"Message: %d %d %d\0A\00"
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define i32 @loop(i32 %a, i32 %b)
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{
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; CHECK: loop:
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entry:
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br label %loop_outer
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loop_outer:
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%outer.0 = phi i32 [ 0, %entry ], [ %outer.2, %loop_outer_finish ]
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br label %loop_inner
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loop_inner:
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%inner.0 = phi i32 [ %a, %loop_outer ], [ %inner.3, %loop_inner_finish ]
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%inner.1 = phi i32 [ %b, %loop_outer ], [ %inner.4, %loop_inner_finish ]
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%inner.2 = phi i32 [ 0, %loop_outer ], [ %inner.5, %loop_inner_finish ]
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%inner.3 = add i32 %inner.0, %inner.1
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%inner.4 = mul i32 %inner.2, 11
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br label %loop_inner_finish
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loop_inner_finish:
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%inner.5 = add i32 %inner.2, 1
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; CHECK: addi {{.*, 1}}
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call i32 (i8*,...)* @printf( i8* getelementptr([19 x i8]* @MSG,i32 0,i32 0),
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i32 %inner.0, i32 %inner.1, i32 %inner.2 )
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; CHECK: brlid
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%inner.6 = icmp eq i32 %inner.5, 100
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; CHECK: cmp
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br i1 %inner.6, label %loop_inner, label %loop_outer_finish
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; CHECK: {{beq|bne}}
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loop_outer_finish:
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%outer.1 = add i32 %outer.0, 1
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%outer.2 = urem i32 %outer.1, 1500
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br label %loop_outer
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; CHECK: br
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}
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