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This patch adds support for the following new instructions in the Power ISA 2.07: vpksdss vpksdus vpkudus vpkudum vupkhsw vupklsw These instructions are available through the vec_packs, vec_packsu, vec_unpackh, and vec_unpackl built-in interfaces. These are lane-sensitive instructions, so the built-ins have different implementations for big- and little-endian, and the instructions must be marked as killing the vector swap optimization for now. The first three instructions perform saturating pack operations. The fourth performs a modulo pack operation, which means it can be represented with a vector shuffle, and conversely the appropriate vector shuffles may cause this instruction to be generated. The other instructions are only generated via built-in support for now. Appropriate tests have been added. There is a companion patch to clang for the rest of this support. llvm-svn: 237499
27 lines
1.3 KiB
ArmAsm
27 lines
1.3 KiB
ArmAsm
# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
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# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
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# CHECK-BE: vpksdss 2, 3, 4 # encoding: [0x10,0x43,0x25,0xce]
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# CHECK-LE: vpksdss 2, 3, 4 # encoding: [0xce,0x25,0x43,0x10]
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vpksdss 2, 3, 4
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# CHECK-BE: vpksdus 2, 3, 4 # encoding: [0x10,0x43,0x25,0x4e]
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# CHECK-LE: vpksdus 2, 3, 4 # encoding: [0x4e,0x25,0x43,0x10]
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vpksdus 2, 3, 4
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# CHECK-BE: vpkudus 2, 3, 4 # encoding: [0x10,0x43,0x24,0xce]
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# CHECK-LE: vpkudus 2, 3, 4 # encoding: [0xce,0x24,0x43,0x10]
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vpkudus 2, 3, 4
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# CHECK-BE: vpkudum 2, 3, 4 # encoding: [0x10,0x43,0x24,0x4e]
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# CHECK-LE: vpkudum 2, 3, 4 # encoding: [0x4e,0x24,0x43,0x10]
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vpkudum 2, 3, 4
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# CHECK-BE: vupkhsw 2, 3 # encoding: [0x10,0x40,0x1e,0x4e]
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# CHECK-LE: vupkhsw 2, 3 # encoding: [0x4e,0x1e,0x40,0x10]
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vupkhsw 2, 3
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# CHECK-BE: vupklsw 2, 3 # encoding: [0x10,0x40,0x1e,0xce]
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# CHECK-LE: vupklsw 2, 3 # encoding: [0xce,0x1e,0x40,0x10]
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vupklsw 2, 3
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