Alex Bradbury dcf62df83b [RISCV] Add codegen support for RV64A ... In order to support codegen RV64A, this patch: * Introduces masked atomics intrinsics for atomicrmw operations and cmpxchg that use the i64 type. These are ultimately lowered to masked operations using lr.w/sc.w, but we need to use these alternate intrinsics for RV64 because i32 is not legal * Modifies RISCVExpandPseudoInsts.cpp to handle PseudoAtomicLoadNand64 and PseudoCmpXchg64 * Modifies the AtomicExpandPass hooks in RISCVTargetLowering to sext/trunc as needed for RV64 and to select the i64 intrinsic IDs when necessary * Adds appropriate patterns to RISCVInstrInfoA.td * Updates test/CodeGen/RISCV/atomic-*.ll to show RV64A support This ends up being a fairly mechanical change, as the logic for RV32A is effectively reused. Differential Revision: https://reviews.llvm.org/D53233 llvm-svn: 351422		2019-01-17 10:04:39 +00:00
..
AsmParser	[RISCV][MC] Add support for evaluating constant symbols as immediates	2019-01-10 15:33:17 +00:00
Disassembler
InstPrinter
MCTargetDesc	[RISCV] Properly evaluate fixup_riscv_pcrel_lo12	2018-12-20 14:52:15 +00:00
TargetInfo
Utils	[RISCV][NFC] Define and use the new CA instruction format	2018-11-16 10:33:23 +00:00
CMakeLists.txt
LLVMBuild.txt
RISCV.h
RISCV.td
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVExpandPseudoInsts.cpp	[RISCV] Add codegen support for RV64A	2019-01-17 10:04:39 +00:00
RISCVFrameLowering.cpp
RISCVFrameLowering.h
RISCVInstrFormats.td	[RISCV][NFC] Define and use the new CA instruction format	2018-11-16 10:33:23 +00:00
RISCVInstrFormatsC.td	[RISCV][NFC] Define and use the new CA instruction format	2018-11-16 10:33:23 +00:00
RISCVInstrInfo.cpp
RISCVInstrInfo.h
RISCVInstrInfo.td	[RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions	2019-01-12 07:32:31 +00:00
RISCVInstrInfoA.td	[RISCV] Add codegen support for RV64A	2019-01-17 10:04:39 +00:00
RISCVInstrInfoC.td	[RISCV] Add UNIMP instruction (32- and 16-bit forms)	2018-11-30 13:39:17 +00:00
RISCVInstrInfoD.td	[RISCV] Add support for the various RISC-V FMA instruction variants	2018-12-13 10:49:05 +00:00
RISCVInstrInfoF.td	[RISCV] Add support for the various RISC-V FMA instruction variants	2018-12-13 10:49:05 +00:00
RISCVInstrInfoM.td	[RISCV] Introduce codegen patterns for RV64M-only instructions	2019-01-12 07:43:06 +00:00
RISCVISelDAGToDAG.cpp	[RISCV] Introduce codegen patterns for instructions introduced in RV64I	2018-11-30 09:38:44 +00:00
RISCVISelLowering.cpp	[RISCV] Add codegen support for RV64A	2019-01-17 10:04:39 +00:00
RISCVISelLowering.h	[TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V	2018-11-30 09:56:54 +00:00
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp
RISCVRegisterInfo.cpp
RISCVRegisterInfo.h
RISCVRegisterInfo.td
RISCVSubtarget.cpp
RISCVSubtarget.h
RISCVSystemOperands.td
RISCVTargetMachine.cpp	[Targets] Add errors for tiny and kernel codemodel on targets that don't support them	2018-12-07 12:10:23 +00:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h