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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
26 lines
890 B
LLVM
26 lines
890 B
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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; REQUIRES: asserts
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@G = external global [0 x i32], align 4
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; Check that MMOs are added to epilogue calle-save restore loads so
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; that the store to G is not considered dependant on the callee-save
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; loads.
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;
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; CHECK: Before post-MI-sched:
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; CHECK-LABEL: # Machine code for function test1:
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; CHECK: SU(2): STRWui $wzr
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; CHECK: SU(3): $x21, $x20 = frame-destroy LDPXi $sp, 2
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; CHECK: Predecessors:
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; CHECK-NEXT: SU(0): Out
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; CHECK-NEXT: SU(0): Out
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; CHECK-NEXT: SU(0): Ord
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; CHECK-NEXT: Successors:
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define void @test1() {
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entry:
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tail call void asm sideeffect "nop", "~{x20},~{x21},~{x22},~{x23}"() nounwind
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store i32 0, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @G, i64 0, i64 0), align 4
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ret void
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}
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