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AArch64
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[AArch64] Expand v1i64 and v2i64 ctlz.
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2016-04-26 05:26:51 +00:00 |
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AMDGPU
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[AMDGPU] Reserve VGPRs for trap handler usage if instructed
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2016-04-26 15:43:14 +00:00 |
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ARM
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[ARM] Expand vector ctlz_zero_undef so it becomes ctlz.
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2016-04-26 05:04:37 +00:00 |
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BPF
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CPP
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Generic
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Introduce llvm.load.relative intrinsic.
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2016-04-22 21:18:02 +00:00 |
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Hexagon
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[Tail duplication] Handle source registers with subregisters
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2016-04-26 18:36:34 +00:00 |
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Inputs
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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Lanai
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[lanai] Add subword scheduling itineraries.
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2016-04-20 18:28:55 +00:00 |
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Mips
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[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions
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2016-04-27 11:02:23 +00:00 |
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MIR
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tests: tweak MIR for ARM tests to correct MI issues
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2016-04-26 17:54:21 +00:00 |
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MSP430
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NVPTX
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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PowerPC
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[ppc64] fix bug in prologue that mfocrf's cr operand should be explict state instead of implicit
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2016-04-27 02:59:28 +00:00 |
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SPARC
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[SPARC] [SSP] Add support for LOAD_STACK_GUARD.
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2016-04-26 10:37:14 +00:00 |
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SystemZ
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[SystemZ] [SSP] Add support for LOAD_STACK_GUARD.
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2016-04-24 13:57:49 +00:00 |
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Thumb
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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Thumb2
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ARM: use r7 as the frame-pointer on all MachO targets.
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2016-04-11 22:27:40 +00:00 |
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WebAssembly
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[WebAssembly] Account for implicit operands when computing operand indices.
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2016-04-26 01:40:56 +00:00 |
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WinEH
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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X86
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[X86] Don't assume that MMX extractelts are from index 0.
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2016-04-27 01:35:29 +00:00 |
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XCore
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
