David Goodwin a282690f82 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. ... llvm-svn: 83122		2009-09-30 00:10:16 +00:00
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Alpha	Eliminate more uses of llvm-as and llvm-dis.	2009-09-09 00:09:15 +00:00
ARM	Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.	2009-09-30 00:10:16 +00:00
Blackfin	Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of	2009-09-28 05:28:43 +00:00
CBackend	Eliminate more uses of llvm-as and llvm-dis.	2009-09-09 00:09:15 +00:00
CellSPU	Convert more tests to avoid llvm-as.	2009-09-11 18:36:27 +00:00
CPP	Eliminate more uses of llvm-as and llvm-dis.	2009-09-09 00:09:15 +00:00
Generic	Convert more tests to avoid llvm-as.	2009-09-11 18:36:27 +00:00
Mips	Eliminate more uses of llvm-as and llvm-dis.	2009-09-09 00:09:15 +00:00
MSP430	Allow symbols to start from the digit if target requests it. This allows, e.g. pinning	2009-09-18 16:57:42 +00:00
PIC16	Eliminate more uses of llvm-as and llvm-dis.	2009-09-09 00:09:15 +00:00
PowerPC	Add nounwind to this test.	2009-09-24 20:20:08 +00:00
SPARC	several major improvements to the sparc backend: support for weak linkage	2009-09-15 17:46:24 +00:00
SystemZ	Eliminate more uses of llvm-as and llvm-dis.	2009-09-09 00:09:15 +00:00
Thumb	Eliminate more uses of llvm-as and llvm-dis.	2009-09-09 00:09:15 +00:00
Thumb2	Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo	2009-09-28 09:14:39 +00:00
X86	Add a CHECK line to check the position of the second divsd.	2009-09-28 20:48:39 +00:00
XCore	Eliminate more uses of llvm-as and llvm-dis.	2009-09-09 00:09:15 +00:00