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9fd29cce52
This adds IR intrinsics for the AArch64 dot-product instructions introduced in v8.2-A. Differential revisioon: https://reviews.llvm.org/D46107 llvm-svn: 331036
127 lines
5.4 KiB
LLVM
127 lines
5.4 KiB
LLVM
; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s
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declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
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declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
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declare <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
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declare <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
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define <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdot_u32:
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; CHECK: udot v0.2s, v1.8b, v2.8b
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdotq_u32:
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; CHECK: udot v0.4s, v1.16b, v2.16b
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdot_s32:
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; CHECK: sdot v0.2s, v1.8b, v2.8b
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdotq_s32:
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; CHECK: sdot v0.4s, v1.16b, v2.16b
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_lane_u32:
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; CHECK: udot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_lane_u32:
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; CHECK: udot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_laneq_u32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_laneq_u32:
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; CHECK: udot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_laneq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_laneq_u32:
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; CHECK: udot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_lane_s32:
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; CHECK: sdot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_lane_s32:
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; CHECK: sdot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_laneq_s32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_laneq_s32:
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; CHECK: sdot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_laneq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_laneq_s32:
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; CHECK: sdot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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