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llvm-mirror/test/MC/Disassembler
2015-10-06 10:08:14 +00:00
..
AArch64 [MC layer][AArch64] llvm-mc accepts 4-bit immediate values for 2015-10-05 13:42:31 +00:00
ARM
Hexagon [Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly. 2015-06-10 16:52:32 +00:00
Mips [mips][disassembler] Changed CHECK-EB directives to CHECK so div/divu are tested. 2015-10-06 10:08:14 +00:00
PowerPC Scalar to vector conversions using direct moves 2015-08-13 17:40:44 +00:00
Sparc [Sparc] Implement i64 load/store support for 32-bit sparc. 2015-08-10 19:11:39 +00:00
SystemZ [SystemZ] Add assembly instructions for obtaining clock values as well as CPU features 2015-10-01 14:43:48 +00:00
X86 [llvm-mc] Ignore opcode size prefix in 64-bit CALL disassembly 2015-08-26 16:20:29 +00:00
XCore