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llvm-mirror/test/CodeGen/AMDGPU/fold-cndmask.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

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# RUN: llc -march=amdgcn -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
# CHECK: %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# CHECK: %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# CHECK: %4:vgpr_32 = COPY %3
# CHECK: %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# CHECK: %6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# CHECK: %7:vgpr_32 = COPY %3
---
name: fold_cndmask
tracksRegLiveness: true
registers:
- { id: 0, class: sgpr_64 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
- { id: 4, class: vgpr_32 }
- { id: 5, class: vgpr_32 }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
body: |
bb.0.entry:
%0 = IMPLICIT_DEF
%1 = V_CNDMASK_B32_e64 0, 0, %0, implicit $exec
%2 = V_CNDMASK_B32_e64 %1, %1, %0, implicit $exec
%3 = IMPLICIT_DEF
%4 = V_CNDMASK_B32_e64 %3, %3, %0, implicit $exec
%5 = COPY %1
%6 = V_CNDMASK_B32_e64 %5, 0, %0, implicit $exec
$vcc = IMPLICIT_DEF
%7 = V_CNDMASK_B32_e32 %3, %3, implicit $exec, implicit $vcc
...