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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
132 lines
3.5 KiB
YAML
132 lines
3.5 KiB
YAML
# RUN: llc -march=amdgcn -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s
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# GCN: bb.0.entry:
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 65536
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 65536
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.1:
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.2:
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# GCN: SI_INIT_M0 65536
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.3:
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# GCN: SI_INIT_M0 3
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# GCN: bb.4:
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# GCN-NOT: SI_INIT_M0
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# GCN: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 4
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.5:
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# GCN-NOT: SI_INIT_M0
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# GCN: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 4
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.6:
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# GCN: SI_INIT_M0 -1,
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# GCN-NEXT: DS_WRITE_B32
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# GCN: SI_INIT_M0 %2
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 %2
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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---
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name: test
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: sreg_32_xm0 }
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body: |
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bb.0.entry:
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successors: %bb.1, %bb.2
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.2
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.4, %bb.5
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S_CBRANCH_VCCZ %bb.4, implicit undef $vcc
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S_BRANCH %bb.5
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bb.4:
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successors: %bb.6
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SI_INIT_M0 3, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 4, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.6
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bb.5:
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successors: %bb.6
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SI_INIT_M0 3, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 4, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.6
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bb.6:
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successors: %bb.0.entry, %bb.6
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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%2 = IMPLICIT_DEF
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SI_INIT_M0 %2, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 %2, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_CBRANCH_VCCZ %bb.6, implicit undef $vcc
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S_BRANCH %bb.0.entry
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...
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