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llvm-mirror/test/MC
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Craig Topper cd0ce7740e [X86] Fix XSAVE64 and similar instructions to not be allowed by the assembler in 32-bit mode. 
There was a top level "let Predicates =" in the .td file that was overriding the Requires on each instruction.

I've added an assert to the code emitter to catch more cases like this. I'm sure this isn't the only place where the right predicates aren't being applied. This assert already found that we don't block btq/btsq/btrq in 32-bit mode.

llvm-svn: 320830
2017-12-15 17:22:58 +00:00
..
AArch64 Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand. 2017-12-14 16:09:48 +00:00
AMDGPU [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma 2017-12-11 15:23:20 +00:00
ARM [DWARFv5] Emit v5 line table header. 2017-12-05 20:35:00 +00:00
AsmParser [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
AVR [AVR] Implement some missing code paths 2017-12-11 11:01:27 +00:00
BPF bpf: print backward branch target properly 2017-11-16 19:15:36 +00:00
COFF [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
Disassembler AMDGPU: Partially fix disassembly of MIMG instructions 2017-12-13 21:07:51 +00:00
ELF Re-submit r289925 (Update .debug_line section version to match DWARF version) 2017-12-04 21:27:46 +00:00
Hexagon [Hexagon] Add support for Hexagon V65 2017-12-11 18:57:54 +00:00
Lanai
MachO [MC] Allow .file directives to be out-of-order 2017-12-14 18:46:43 +00:00
Markup
Mips [mips] Removal of microMIPS64R6 2017-12-11 11:21:40 +00:00
PowerPC PowerPC: support external pid instructions in MC layer. 2017-12-10 08:43:19 +00:00
RISCV [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero 2017-12-15 10:20:51 +00:00
Sparc [Sparc] invalid adjustments in TLS_LE/TLS_LDO relocations removed 2017-07-25 15:28:28 +00:00
SystemZ
WebAssembly [WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtors 2017-12-15 00:17:10 +00:00
X86 [X86] Fix XSAVE64 and similar instructions to not be allowed by the assembler in 32-bit mode. 2017-12-15 17:22:58 +00:00