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llvm-mirror/test/MC/Disassembler
Matt Arsenault e25266fd34 AMDGPU: Partially fix disassembly of MIMG instructions
Stores failed to decode at all since they didn't have a
DecoderNamespace set. Loads worked, but did not change
the register width displayed to match the numbmer of
enabled channels.

The number of printed registers for vaddr is still wrong,
but I don't think that's encoded in the instruction so
there's not much we can do about that.

Image atomics are still broken. MIMG is the same
encoding for SI/VI, but the image atomic classes
are split up into encoding specific versions unlike
every other MIMG instruction. They have isAsmParserOnly
set on them for some reason. dmask is also special for
these, so we probably should not have it as an explicit
operand as it is now.

llvm-svn: 320614
2017-12-13 21:07:51 +00:00
..
AArch64 [AArch64][TableGen] Skip tied result operands for InstAlias 2017-11-20 14:36:40 +00:00
AMDGPU AMDGPU: Partially fix disassembly of MIMG instructions 2017-12-13 21:07:51 +00:00
ARC [ARC] Add instruction subset for the ARC backend. 2017-12-02 05:25:17 +00:00
ARM [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode 2017-10-18 14:47:37 +00:00
Hexagon [Hexagon] Remove trailing spaces, NFC 2017-11-22 20:43:00 +00:00
Lanai
Mips [mips] Removal of microMIPS64R6 2017-12-11 11:21:40 +00:00
PowerPC PowerPC: support external pid instructions in MC layer. 2017-12-10 08:43:19 +00:00
Sparc
SystemZ [SystemZ] Add support for IBM z14 processor (3/3) 2017-07-17 17:44:20 +00:00
X86 Avoid unecessary opsize byte in segment move to memory 2017-11-21 19:28:13 +00:00
XCore