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1c11c23080
Summary: This also removes the need for atomic pseudo instructions, since we select the correct encoding directly in SITargetLowering::lowerImage for dimension-aware image intrinsics. Mesa uses dimension-aware image intrinsics since commit a9a7993441. Change-Id: I7473d20009476a4ed6d919cae4e6dca9ff42e77a Reviewers: arsenm, rampitec, mareko, tpr, b-sumner Subscribers: kzhuravl, wdng, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D48167 llvm-svn: 335231
78 lines
2.9 KiB
TableGen
78 lines
2.9 KiB
TableGen
//===-- AMDGPUSearchableTables.td - ------------------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Resource intrinsics table.
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//===----------------------------------------------------------------------===//
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class RsrcIntrinsic<AMDGPURsrcIntrinsic intr> {
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Intrinsic Intr = !cast<Intrinsic>(intr);
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bits<8> RsrcArg = intr.RsrcArg;
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bit IsImage = intr.IsImage;
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}
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def RsrcIntrinsics : GenericTable {
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let FilterClass = "RsrcIntrinsic";
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let Fields = ["Intr", "RsrcArg", "IsImage"];
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let PrimaryKey = ["Intr"];
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let PrimaryKeyName = "lookupRsrcIntrinsic";
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}
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foreach intr = !listconcat(AMDGPUBufferIntrinsics,
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AMDGPUImageDimIntrinsics,
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AMDGPUImageDimAtomicIntrinsics) in {
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def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
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}
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class SourceOfDivergence<Intrinsic intr> {
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Intrinsic Intr = intr;
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}
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def SourcesOfDivergence : GenericTable {
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let FilterClass = "SourceOfDivergence";
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let Fields = ["Intr"];
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let PrimaryKey = ["Intr"];
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let PrimaryKeyName = "lookupSourceOfDivergence";
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}
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def : SourceOfDivergence<int_amdgcn_workitem_id_x>;
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def : SourceOfDivergence<int_amdgcn_workitem_id_y>;
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def : SourceOfDivergence<int_amdgcn_workitem_id_z>;
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def : SourceOfDivergence<int_amdgcn_interp_mov>;
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def : SourceOfDivergence<int_amdgcn_interp_p1>;
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def : SourceOfDivergence<int_amdgcn_interp_p2>;
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def : SourceOfDivergence<int_amdgcn_mbcnt_hi>;
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def : SourceOfDivergence<int_amdgcn_mbcnt_lo>;
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def : SourceOfDivergence<int_r600_read_tidig_x>;
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def : SourceOfDivergence<int_r600_read_tidig_y>;
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def : SourceOfDivergence<int_r600_read_tidig_z>;
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def : SourceOfDivergence<int_amdgcn_atomic_inc>;
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def : SourceOfDivergence<int_amdgcn_atomic_dec>;
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def : SourceOfDivergence<int_amdgcn_ds_fadd>;
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def : SourceOfDivergence<int_amdgcn_ds_fmin>;
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def : SourceOfDivergence<int_amdgcn_ds_fmax>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_swap>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_add>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_sub>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_smin>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_umin>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_smax>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_umax>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_and>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_or>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_xor>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_cmpswap>;
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def : SourceOfDivergence<int_amdgcn_ps_live>;
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def : SourceOfDivergence<int_amdgcn_ds_swizzle>;
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foreach intr = AMDGPUImageDimAtomicIntrinsics in
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def : SourceOfDivergence<intr>;
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