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llvm-mirror/lib/Target/AMDGPU
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Stanislav Mekhanoshin 57e6f6b2ef Remove check for single use in ShrinkDemandedConstant 
This removes check for single use from general ShrinkDemandedConstant
to the BE because of the AArch64 regression after D56289/rL350475.

After several hours of experiments I did not come up with a testcase
failing on any other targets if check is not performed.

Moreover, direct call to ShrinkDemandedConstant is not really needed
and superceed by SimplifyDemandedBits.

Differential Revision: https://reviews.llvm.org/D56406

llvm-svn: 350684
2019-01-09 02:24:22 +00:00
..
AsmParser [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
Disassembler AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
InstPrinter AMDGPU: Re-apply r341982 after fixing the layering issue 2018-09-12 18:50:47 +00:00
MCTargetDesc AMDGPU: Use an ABS32_LO relocation for SCRATCH_RSRC_DWORD1 2018-12-19 11:55:03 +00:00
TargetInfo
Utils [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
AMDGPU.h [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
AMDGPU.td AMDGPU: Remove llvm.AMDGPU.kill 2018-12-07 17:46:16 +00:00
AMDGPUAliasAnalysis.cpp Allow subclassing ExternalAA 2018-11-07 20:26:42 +00:00
AMDGPUAliasAnalysis.h Allow subclassing ExternalAA 2018-11-07 20:26:42 +00:00
AMDGPUAlwaysInlinePass.cpp AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUAnnotateKernelFeatures.cpp Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attribute 2018-12-13 21:23:12 +00:00
AMDGPUAnnotateUniformValues.cpp AMDGPU: test for uniformity of branch instruction, not its condition 2019-01-07 15:52:28 +00:00
AMDGPUArgumentUsageInfo.cpp AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z 2018-06-21 18:36:04 +00:00
AMDGPUArgumentUsageInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUAsmPrinter.cpp [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
AMDGPUAsmPrinter.h [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
AMDGPUAtomicOptimizer.cpp [AMDGPU] Fix the new atomic optimizer in pixel shaders. 2018-11-05 12:04:48 +00:00
AMDGPUCallingConv.td AMDGPU: Partially fix handling of packed amdgpu_ps arguments 2018-08-01 19:57:34 +00:00
AMDGPUCallLowering.cpp AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUCallLowering.h AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUCodeGenPrepare.cpp [IRBuilder] Fixup CreateIntrinsic to allow specifying Types to Mangle. 2018-10-08 10:32:33 +00:00
AMDGPUFeatures.td AMDGPU: Allow fp32-denormals feature for r600 targets 2018-08-01 15:04:36 +00:00
AMDGPUFixFunctionBitcasts.cpp [AMDGPU] Add a pass to promote bitcast calls 2018-10-26 13:18:36 +00:00
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUGenRegisterBankInfo.def AMDGPU/GlobalISel: Introduce vcc reg bank 2019-01-08 06:30:53 +00:00
AMDGPUGISel.td AMDGPU/GlobalISel: Select amdgcn.cvt.pkrtz to 64-bit instructions 2018-10-08 17:49:29 +00:00
AMDGPUHSAMetadataStreamer.cpp [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
AMDGPUHSAMetadataStreamer.h [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
AMDGPUInline.cpp fix typos aggressively; NFC 2018-11-07 14:35:36 +00:00
AMDGPUInstrInfo.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUInstrInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUInstrInfo.td AMDGPU: Remove PHI loop condition optimization 2018-10-31 13:26:48 +00:00
AMDGPUInstructions.td [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
AMDGPUInstructionSelector.cpp Revert "AMDGPU/GlobalISel: Implement select for G_INSERT" 2018-10-11 23:36:46 +00:00
AMDGPUInstructionSelector.h Revert "AMDGPU/GlobalISel: Implement select for G_INSERT" 2018-10-11 23:36:46 +00:00
AMDGPUIntrinsicInfo.cpp AMDGPU: Remove llvm.AMDGPU.kill 2018-12-07 17:46:16 +00:00
AMDGPUIntrinsicInfo.h AMDGPU: Remove llvm.AMDGPU.kill 2018-12-07 17:46:16 +00:00
AMDGPUISelDAGToDAG.cpp AMDGPU: Don't peel of the offset if the resulting base could possibly be negative in Indirect addressing. 2018-12-21 20:57:34 +00:00
AMDGPUISelLowering.cpp [TargetLowering][AMDGPU] Remove the SimplifyDemandedBits function that takes a User and OpIdx. Stop using it in AMDGPU target for simplifyI24. 2019-01-07 19:30:43 +00:00
AMDGPUISelLowering.h DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
AMDGPULegalizerInfo.cpp AMDGPU/GlobalISel: Legalize concat_vectors 2019-01-08 01:30:02 +00:00
AMDGPULegalizerInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPULibCalls.cpp AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPULibFunc.cpp [AMDGPU] Fix discarded result of addAttribute 2018-12-09 21:56:50 +00:00
AMDGPULibFunc.h AMDGPU: Fix missing C++ mode comment 2018-06-20 19:45:40 +00:00
AMDGPULowerIntrinsics.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPULowerKernelArguments.cpp AMDGPU: Fix offsets for < 4-byte aggregate kernel arguments 2018-12-07 22:12:17 +00:00
AMDGPULowerKernelAttributes.cpp AMDGPU: Add pass to optimize reqd_work_group_size 2018-05-18 21:35:00 +00:00
AMDGPUMachineCFGStructurizer.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUMachineFunction.cpp Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
AMDGPUMachineFunction.h Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
AMDGPUMachineModuleInfo.cpp
AMDGPUMachineModuleInfo.h
AMDGPUMacroFusion.cpp [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx 2018-11-09 17:58:59 +00:00
AMDGPUMacroFusion.h
AMDGPUMCInstLower.cpp AMDGPU: Fix getInstSizeInBytes 2018-08-29 07:46:09 +00:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp [AMDGPU] Change enqueue kernel handle type 2018-06-13 17:31:51 +00:00
AMDGPUPerfHintAnalysis.cpp AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUPerfHintAnalysis.h Fix -Winconsistent-missing-overrides in AMDGPU code 2018-05-25 17:46:24 +00:00
AMDGPUPromoteAlloca.cpp [AMDGPU] Extend promote alloca vectorization 2018-11-08 00:16:23 +00:00
AMDGPUPTNote.h [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
AMDGPURegAsmNames.inc.cpp
AMDGPURegisterBankInfo.cpp AMDGPU/GlobalISel: Introduce vcc reg bank 2019-01-08 06:30:53 +00:00
AMDGPURegisterBankInfo.h AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg 2018-12-20 00:33:49 +00:00
AMDGPURegisterBanks.td AMDGPU/GlobalISel: Introduce vcc reg bank 2019-01-08 06:30:53 +00:00
AMDGPURegisterInfo.cpp AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers 2018-05-22 02:03:23 +00:00
AMDGPURegisterInfo.h [TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints() 2018-10-05 14:23:11 +00:00
AMDGPURegisterInfo.td AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
AMDGPURewriteOutArguments.cpp
AMDGPUSearchableTables.td AMDGPU: Remove old-style image intrinsics 2018-06-21 13:37:45 +00:00
AMDGPUSubtarget.cpp Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" 2018-11-29 20:14:17 +00:00
AMDGPUSubtarget.h Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" 2018-11-29 20:14:17 +00:00
AMDGPUTargetMachine.cpp Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attribute 2018-12-13 21:23:12 +00:00
AMDGPUTargetMachine.h AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUTargetObjectFile.cpp [AMDGPU] Change section name with metadata access 2019-01-03 11:22:58 +00:00
AMDGPUTargetObjectFile.h [AMDGPU] Set metadata access for explicit section 2018-12-12 11:20:04 +00:00
AMDGPUTargetTransformInfo.cpp AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUTargetTransformInfo.h AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUUnifyDivergentExitNodes.cpp [NFC] Rename the DivergenceAnalysis to LegacyDivergenceAnalysis 2018-08-30 14:21:36 +00:00
AMDGPUUnifyMetadata.cpp
AMDILCFGStructurizer.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
AMDKernelCodeT.h
BUFInstructions.td [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
CaymanInstructions.td
CMakeLists.txt [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
DSInstructions.td AMDGPU: Avoid selecting ds_{read,write}2_b32 on SI 2018-10-17 15:37:48 +00:00
EvergreenInstructions.td AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
FLATInstructions.td [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST 2018-11-16 01:13:34 +00:00
GCNDPPCombine.cpp [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) 2018-11-30 14:21:56 +00:00
GCNHazardRecognizer.cpp [AMDGPU] Prevent sequences of non-instructions disrupting GCNHazardRecognizer wait state counting 2018-09-10 10:14:48 +00:00
GCNHazardRecognizer.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNILPSched.cpp ScheduleDAG: Cleanup dumping code; NFC 2018-09-19 00:23:35 +00:00
GCNIterativeScheduler.cpp llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) 2018-09-27 02:13:45 +00:00
GCNIterativeScheduler.h
GCNMinRegStrategy.cpp ScheduleDAG: Cleanup dumping code; NFC 2018-09-19 00:23:35 +00:00
GCNProcessors.td [AMDGPU] Defined gfx909 Raven Ridge 2 2018-10-24 08:14:07 +00:00
GCNRegPressure.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNRegPressure.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNSchedStrategy.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNSchedStrategy.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
LLVMBuild.txt [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
MIMGInstructions.td Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" 2018-11-29 20:14:17 +00:00
R600.td Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
R600AsmPrinter.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600AsmPrinter.h AMDGPU: Split R600 AsmPrinter code into its own class 2018-05-24 20:02:01 +00:00
R600ClauseMergePass.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600ControlFlowFinalizer.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx 2018-11-09 17:58:59 +00:00
R600ExpandSpecialInstrs.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600FrameLowering.cpp
R600FrameLowering.h
R600InstrFormats.td AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600InstrInfo.cpp [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx 2018-11-09 17:58:59 +00:00
R600InstrInfo.h [PSV] Update API to be able to use TargetCustom without UB. 2018-08-20 19:23:45 +00:00
R600Instructions.td AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
R600ISelLowering.cpp [SelectionDAG] Add FoldBUILD_VECTOR to simplify new BUILD_VECTOR nodes 2018-10-30 10:32:11 +00:00
R600ISelLowering.h AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS 2018-08-01 18:36:07 +00:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp Fix clang -Wimplicit-fallthrough warnings across llvm, NFC 2018-11-01 19:54:45 +00:00
R600MachineScheduler.h
R600OpenCLImageTypeLoweringPass.cpp
R600OptimizeVectorRegisters.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600Packetizer.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600Processors.td AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600RegisterInfo.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600RegisterInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600RegisterInfo.td AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600Schedule.td
R700Instructions.td AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIAnnotateControlFlow.cpp AMDGPU: test for uniformity of branch instruction, not its condition 2019-01-07 15:52:28 +00:00
SIDebuggerInsertNops.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIDefines.h [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
SIFixSGPRCopies.cpp AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
SIFixupVectorISel.cpp [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
SIFixVGPRCopies.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIFixWWMLiveness.cpp [AMDGPU] Reworked SIFixWWMLiveness 2018-08-02 23:31:32 +00:00
SIFoldOperands.cpp [AMDGPU] Fix scalar operand folding bug that causes SHOC performance regression. 2019-01-03 19:55:32 +00:00
SIFormMemoryClauses.cpp llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) 2018-09-27 02:13:45 +00:00
SIFrameLowering.cpp AMDGPU: Rename isAmdCodeObjectV2 -> isAmdHsaOrMesa 2018-10-04 21:02:16 +00:00
SIFrameLowering.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIInsertSkips.cpp AMDGPU: Fix analyzeBranch failing with pseudoterminators 2018-11-16 05:03:02 +00:00
SIInsertWaitcnts.cpp AMDGPU/InsertWaitcnts: Update VGPR/SGPR bounds when brackets are merged 2018-12-19 10:17:49 +00:00
SIInstrFormats.td [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
SIInstrInfo.cpp [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos 2018-12-03 13:04:54 +00:00
SIInstrInfo.h [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
SIInstrInfo.td [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) 2018-11-30 14:21:56 +00:00
SIInstructions.td AMDGPU: Add patterns for v4i16/v4f16 -> v4i16/v4f16 bitcasts 2018-12-19 22:53:33 +00:00
SIIntrinsics.td AMDGPU: Remove llvm.SI.tbuffer.store 2018-12-07 18:03:47 +00:00
SIISelLowering.cpp Remove check for single use in ShrinkDemandedConstant 2019-01-09 02:24:22 +00:00
SIISelLowering.h [AMDGPU] Promote constant offset to the immediate by finding a new base with 13bit constant offset from the nearby instructions. 2018-12-14 21:13:14 +00:00
SILoadStoreOptimizer.cpp [AMDGPU] Removed the unnecessary operand size-check-assert from processBaseWithConstOffset(). 2018-12-18 19:58:39 +00:00
SILowerControlFlow.cpp AMDGPU: Remove PHI loop condition optimization 2018-10-31 13:26:48 +00:00
SILowerI1Copies.cpp AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
SIMachineFunctionInfo.cpp [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
SIMachineFunctionInfo.h AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z 2018-06-21 18:36:04 +00:00
SIMachineScheduler.cpp [CodeGen][NFC] Make TII::getMemOpBaseImmOfs return a base operand 2018-11-28 12:00:20 +00:00
SIMachineScheduler.h
SIMemoryLegalizer.cpp [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D. 2018-12-10 16:35:53 +00:00
SIModeRegister.cpp [AMDGPU] Add new Mode Register pass - minor fix 2018-12-10 16:23:30 +00:00
SIOptimizeExecMasking.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIOptimizeExecMaskingPreRA.cpp [AMDGPU] Fix build failure, second attempt 2018-12-13 05:52:11 +00:00
SIPeepholeSDWA.cpp [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos 2018-12-03 13:04:54 +00:00
SIProgramInfo.h [AMDGPU] Refactor HSAMetadataStream::emitKernel (NFC) 2018-07-10 17:31:32 +00:00
SIRegisterInfo.cpp [AMDGPU] Simplify negated condition 2018-12-13 03:17:40 +00:00
SIRegisterInfo.h [AMDGPU] Simplify negated condition 2018-12-13 03:17:40 +00:00
SIRegisterInfo.td AMDGPU: Remove v16i8 from register classes 2019-01-07 13:31:55 +00:00
SISchedule.td
SIShrinkInstructions.cpp [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
SIWholeQuadMode.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SMInstructions.td AMDGPU: Allow f32 types for llvm.amdgcn.s.buffer.load 2018-12-07 18:41:39 +00:00
SOPInstructions.td [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
VIInstrFormats.td
VIInstructions.td
VOP1Instructions.td [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
VOP2Instructions.td [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
VOP3Instructions.td [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
VOP3PInstructions.td [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
VOPCInstructions.td AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16 2018-08-15 21:25:20 +00:00
VOPInstructions.td [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) 2018-11-30 14:21:56 +00:00