Jessica Paquette ae291b6dfb [GlobalISel] Add G_SBFX + G_UBFX (bitfield extraction opcodes) ... There is a bunch of similar bitfield extraction code throughout *ISelDAGToDAG. E.g, ARMISelDAGToDAG, AArch64ISelDAGToDAG, and AMDGPUISelDAGToDAG all contain code that matches a bitfield extract from an and + right shift. Rather than duplicating code in the same way, this adds two opcodes: - G_UBFX (unsigned bitfield extract) - G_SBFX (signed bitfield extract) They work like this ``` %x = G_UBFX %y, %lsb, %width ``` Where `lsb` and `width` are - The least-significant bit of the extraction - The width of the extraction This will extract `width` bits from `%y`, starting at `lsb`. G_UBFX zero-extends the result, while G_SBFX sign-extends the result. This should allow us to use the combiner to match the bitfield extraction patterns rather than duplicating pattern-matching code in each target. Differential Revision: https://reviews.llvm.org/D98464		2021-03-19 14:37:19 -07:00
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block-extract.png	[globalisel][docs] Add a section about debugging with the block extractor	2019-11-05 14:48:27 -08:00
GenericOpcode.rst	[GlobalISel] Add G_SBFX + G_UBFX (bitfield extraction opcodes)	2021-03-19 14:37:19 -07:00
GMIR.rst	[docs] Fix typos	2020-08-09 19:31:49 -07:00
index.rst	[globalisel][docs] Rework GMIR documentation and add an early GenericOpcode reference	2019-11-05 15:16:43 -08:00
InstructionSelect.rst
IRTranslator.rst	Update references to 'master' branch.	2020-12-21 19:10:34 +00:00
KnownBits.rst	Doc: Links should use https	2020-03-22 22:49:33 +01:00
Legalizer.rst	GlobalISel: Make type for lower action more consistently optional	2020-08-17 16:24:55 -04:00
pipeline-overview-customized.png
pipeline-overview-with-combiners.png
pipeline-overview.png
Pipeline.rst	Try to fix sphinx "Could not lex literal_block as "llvm"" warning.	2019-11-09 22:15:26 +00:00
Porting.rst	[globalisel][docs] Add the tutorial to the Porting document	2019-10-30 14:53:39 -07:00
RegBankSelect.rst
Resources.rst
testing-pass-level.png
testing-unit-level.png