Johnny Chen ae5d27987a ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. ... Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. llvm-svn: 128234		2011-03-24 20:42:48 +00:00
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arm-tests.txt	ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.	2011-03-24 20:42:48 +00:00
dg.exp
invalid-CPS3p-arm.txt	Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,	2011-03-24 17:04:22 +00:00
invalid-VLDMSDB-arm.txt	Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,	2011-03-24 17:04:22 +00:00
neon-tests.txt	The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the	2011-03-24 18:40:38 +00:00
thumb-tests.txt	Add disassembly test cases for:	2011-03-22 23:08:56 +00:00