Simon Pilgrim aed4e7449f [X86] combineX86ShuffleChain - ensure we only peek through bitcasts to vectors (PR51858) ... When searching for hidden identity shuffles (added at rG41146bfe82aecc79961c3de898cda02998172e4b), only peek through bitcasts to the source operand if it is a vector type as well. (cherry picked from commit dcba99418438ec1d624ad207674234bd2e9e3394)		2021-09-20 11:22:27 -07:00
..
AArch64	Revert "[AArch64][GlobalISel] Legalize bswap <2 x i16>"	2021-09-10 21:09:59 -07:00
AMDGPU	AMDGPU/GlobalISel: Fix selecting G_SEXTLOAD/G_ZEXTLOAD pre-gfx9	2021-07-27 15:56:42 -04:00
ARC
ARM	[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert	2021-08-18 12:14:24 -07:00
AVR	[AVR] Only support sp, r0 and r1 in llvm.read_register	2021-07-24 14:03:27 +02:00
BPF	BPF: avoid NE/EQ loop exit condition	2021-08-06 12:45:53 -07:00
Generic	[PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX	2021-07-26 23:21:38 +00:00
Hexagon	[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs	2021-07-27 18:36:28 -05:00
Inputs
Lanai
M68k
Mips	Revert [MC][ELF] Emit separate unique sections for different flags	2021-09-10 16:55:29 -07:00
MIR
MSP430
NVPTX
PowerPC	Revert "[HardwareLoops] Change order of SCEV expression construction for InitLoopCount."	2021-09-08 20:46:17 -07:00
RISCV	[RISCV] Fix reporting of incorrect commutable operand indices	2021-09-03 15:48:26 -07:00
SPARC
SystemZ	[SystemZ][z/OS] Initial code to generate assembly files on z/OS	2021-07-27 11:29:15 -04:00
Thumb
Thumb2	[SimplifyCFG] performBranchToCommonDestFolding(): require block-closed SSA form for bonus instructions (PR51125)	2021-09-10 09:02:26 -07:00
VE
WebAssembly	[WebAssembly] Fix FastISel of condition in different block (PR51651)	2021-08-31 20:58:25 -07:00
WinCFGuard
WinEH
X86	[X86] combineX86ShuffleChain - ensure we only peek through bitcasts to vectors (PR51858)	2021-09-20 11:22:27 -07:00
XCore