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https://github.com/RPCS3/llvm-mirror.git
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12eb12a774
The dream of a unified check-line auto-generator for all phases of compilation is dead. The llc script has already diverged to be better at its goal, so having 2 scripts that do almost the same thing is just causing confusion. We can rip out the llc ability in update_test_checks.py next and rename it, so it will be clear that we have one script for llc check auto-generation and another for opt. llvm-svn: 305206
127 lines
4.5 KiB
LLVM
127 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s
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define void @test_x86_sse_storeu_ps(i8* %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse_storeu_ps:
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; SSE: ## BB#0:
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; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; SSE-NEXT: movups %xmm0, (%eax)
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; SSE-NEXT: retl
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;
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; KNL-LABEL: test_x86_sse_storeu_ps:
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; KNL: ## BB#0:
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; KNL-NEXT: movl {{[0-9]+}}(%esp), %eax
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; KNL-NEXT: vmovups %xmm0, (%eax)
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; KNL-NEXT: retl
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; CHECK-LABEL: test_x86_sse_storeu_ps:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movups %xmm0, (%eax)
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; CHECK-NEXT: retl
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call void @llvm.x86.sse.storeu.ps(i8* %a0, <4 x float> %a1)
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ret void
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}
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declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
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define <4 x float> @test_x86_sse_add_ss(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse_add_ss:
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; SSE: ## BB#0:
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; SSE-NEXT: addss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x58,0xc1]
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; SSE-NEXT: retl ## encoding: [0xc3]
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;
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; AVX2-LABEL: test_x86_sse_add_ss:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vaddss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x58,0xc1]
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; AVX2-NEXT: retl ## encoding: [0xc3]
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;
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; SKX-LABEL: test_x86_sse_add_ss:
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; SKX: ## BB#0:
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; SKX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7e,0x08,0x58,0xc1]
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; SKX-NEXT: retl ## encoding: [0xc3]
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; CHECK-LABEL: test_x86_sse_add_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: addss %xmm1, %xmm0
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; CHECK-NEXT: retl
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%res = call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_sub_ss(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse_sub_ss:
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; SSE: ## BB#0:
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; SSE-NEXT: subss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x5c,0xc1]
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; SSE-NEXT: retl ## encoding: [0xc3]
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;
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; AVX2-LABEL: test_x86_sse_sub_ss:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vsubss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x5c,0xc1]
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; AVX2-NEXT: retl ## encoding: [0xc3]
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;
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; SKX-LABEL: test_x86_sse_sub_ss:
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; SKX: ## BB#0:
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; SKX-NEXT: vsubss %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7e,0x08,0x5c,0xc1]
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; SKX-NEXT: retl ## encoding: [0xc3]
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; CHECK-LABEL: test_x86_sse_sub_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: subss %xmm1, %xmm0
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; CHECK-NEXT: retl
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%res = call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_mul_ss(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse_mul_ss:
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; SSE: ## BB#0:
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; SSE-NEXT: mulss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x59,0xc1]
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; SSE-NEXT: retl ## encoding: [0xc3]
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;
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; AVX2-LABEL: test_x86_sse_mul_ss:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vmulss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x59,0xc1]
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; AVX2-NEXT: retl ## encoding: [0xc3]
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;
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; SKX-LABEL: test_x86_sse_mul_ss:
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; SKX: ## BB#0:
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; SKX-NEXT: vmulss %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7e,0x08,0x59,0xc1]
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; SKX-NEXT: retl ## encoding: [0xc3]
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; CHECK-LABEL: test_x86_sse_mul_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: mulss %xmm1, %xmm0
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; CHECK-NEXT: retl
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%res = call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_div_ss(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse_div_ss:
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; SSE: ## BB#0:
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; SSE-NEXT: divss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x5e,0xc1]
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; SSE-NEXT: retl ## encoding: [0xc3]
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;
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; AVX2-LABEL: test_x86_sse_div_ss:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vdivss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x5e,0xc1]
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; AVX2-NEXT: retl ## encoding: [0xc3]
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;
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; SKX-LABEL: test_x86_sse_div_ss:
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; SKX: ## BB#0:
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; SKX-NEXT: vdivss %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7e,0x08,0x5e,0xc1]
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; SKX-NEXT: retl ## encoding: [0xc3]
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; CHECK-LABEL: test_x86_sse_div_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: divss %xmm1, %xmm0
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; CHECK-NEXT: retl
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%res = call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.div.ss(<4 x float>, <4 x float>) nounwind readnone
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