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llvm-mirror/include/llvm/Target
Simon Cook bae1c75f0d [TableGen] Support combining AssemblerPredicates with ORs
For context, the proposed RISC-V bit manipulation extension has a subset
of instructions which require one of two SubtargetFeatures to be
enabled, 'zbb' or 'zbp', and there is no defined feature which both of
these can imply to use as a constraint either (see comments in D65649).

AssemblerPredicates allow multiple SubtargetFeatures to be declared in
the "AssemblerCondString" field, separated by commas, and this means
that the two features must both be enabled. There is no equivalent to
say that _either_ feature X or feature Y must be enabled, short of
creating a dummy SubtargetFeature for this purpose and having features X
and Y imply the new feature.

To solve the case where X or Y is needed without adding a new feature,
and to better match a typical TableGen style, this replaces the existing
"AssemblerCondString" with a dag "AssemblerCondDag" which represents the
same information. Two operators are defined for use with
AssemblerCondDag, "all_of", which matches the current behaviour, and
"any_of", which adds the new proposed ORing features functionality.

This was originally proposed in the RFC at
http://lists.llvm.org/pipermail/llvm-dev/2020-February/139138.html

Changes to all current backends are mechanical to support the replaced
functionality, and are NFCI.

At this stage, it is illegal to combine features with ands and ors in a
single AssemblerCondDag. I suspect this case is sufficiently rare that
adding more complex changes to support it are unnecessary.

Differential Revision: https://reviews.llvm.org/D74338
2020-03-13 17:13:51 +00:00
..
GlobalISel [GlobalISel] Add new combine to convert scalar G_MUL to G_SHL. 2020-01-29 13:39:00 -08:00
CodeGenCWrappers.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
GenericOpcodes.td GlobalISel: Assume G_INTRINSIC* are convergent 2020-02-05 10:17:22 -08:00
Target.td [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
TargetCallingConv.td Add Windows Control Flow Guard checks (/guard:cf). 2019-10-28 15:19:39 +00:00
TargetInstrPredicate.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
TargetIntrinsicInfo.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
TargetItinerary.td [DFAPacketizer] Allow namespacing of automata per-itinerary 2019-08-30 19:50:49 +00:00
TargetLoweringObjectFile.h [NFC][XCOFF] Refactor Csect creation into TargetLoweringObjectFile 2020-01-22 12:09:11 -05:00
TargetMachine.h [VE] Target-specific bit size for sjljehprepare 2020-03-10 17:51:16 +01:00
TargetOptions.h Reland "[DebugInfo] Enable the debug entry values feature by default" 2020-03-10 09:15:06 +01:00
TargetPfmCounters.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
TargetSchedule.td [Tblgen][MCA] Add the ability to mark groups as LoadQueue and StoreQueue. NFCI 2019-08-27 18:20:34 +00:00
TargetSelectionDAG.td [Intrinsic] Add fixed point saturating division intrinsics. 2020-02-24 10:50:52 +01:00