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llvm-mirror/test/CodeGen/Hexagon/opt-fabs.ll
Krzysztof Parzyszek 4625bb8dfb [Hexagon] Bit-based instruction simplification
Analyze bit patterns of operands and values of instructions to perform
various simplifications, dead/redundant code elimination, etc.

llvm-svn: 250868
2015-10-20 22:57:13 +00:00

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441 B
LLVM

; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=hexagonv5 -hexagon-bit=0 < %s | FileCheck %s
; Optimize fabsf to clrbit in V5.
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
define float @my_fabsf(float %x) nounwind {
entry:
%x.addr = alloca float, align 4
store float %x, float* %x.addr, align 4
%0 = load float, float* %x.addr, align 4
%call = call float @fabsf(float %0) readnone
ret float %call
}
declare float @fabsf(float)