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851e2f985f
https://reviews.llvm.org/D24924 This improves the code generated for a sequence of AND, ANY_EXT, SRL instructions. This is a targetted fix for this special pattern. The pattern is generated by target independet dag combiner and so a more general fix may not be necessary. If we come across other similar cases, some ideas for handling it are discussed on the code review. llvm-svn: 284983
30 lines
904 B
LLVM
30 lines
904 B
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s
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%class.PB2 = type { [1 x i32], %class.PB1* }
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%class.PB1 = type { [1 x i32], i64, i64, i32 }
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; Function Attrs: norecurse nounwind readonly
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define zeroext i1 @foo(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr {
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entry:
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%arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
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%0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
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%and.i = and i32 %0, 8
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%cmp.i = icmp ne i32 %and.i, 0
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%arrayidx.i37 = bitcast %class.PB2* %s_b to i32*
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%1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1
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%and.i4 = and i32 %1, 8
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%cmp.i5 = icmp ne i32 %and.i4, 0
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%cmp = xor i1 %cmp.i, %cmp.i5
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ret i1 %cmp
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; CHECK-LABEL: @foo
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; CHECK: rldicl {{[0-9]+}}, {{[0-9]+}}, 61, 63
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}
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!1 = !{!2, !2, i64 0}
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!2 = !{!"int", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C++ TBAA"}
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