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1b981ebf72
Summary: RISC-V uses a post-select peephole pass to optimise `(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`. This peephole wasn't firing for accesses to constant pools, which is how we materialise most floating point constants. This adds support for the constantpool case, which improves code generation for lots of small FP loading examples. I have not added any tests because this structure is well-covered by the `fp-imm.ll` testcases, as well as almost all other uses of floating point constants in the RISC-V backend tests. Reviewed By: luismarques, asb Differential Revision: https://reviews.llvm.org/D79523
45 lines
1.4 KiB
LLVM
45 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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; TODO: constant pool shouldn't be necessary for RV64IF.
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define float @float_imm() nounwind {
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; RV32IF-LABEL: float_imm:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a0, 263313
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; RV32IF-NEXT: addi a0, a0, -37
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: float_imm:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: lui a0, %hi(.LCPI0_0)
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; RV64IF-NEXT: flw ft0, %lo(.LCPI0_0)(a0)
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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ret float 3.14159274101257324218750
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}
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define float @float_imm_op(float %a) nounwind {
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; RV32IF-LABEL: float_imm_op:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a1, %hi(.LCPI1_0)
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; RV32IF-NEXT: flw ft0, %lo(.LCPI1_0)(a1)
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: float_imm_op:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: lui a1, %hi(.LCPI1_0)
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; RV64IF-NEXT: flw ft0, %lo(.LCPI1_0)(a1)
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = fadd float %a, 1.0
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ret float %1
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}
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