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https://github.com/RPCS3/llvm-mirror.git
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1b981ebf72
Summary: RISC-V uses a post-select peephole pass to optimise `(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`. This peephole wasn't firing for accesses to constant pools, which is how we materialise most floating point constants. This adds support for the constantpool case, which improves code generation for lots of small FP loading examples. I have not added any tests because this structure is well-covered by the `fp-imm.ll` testcases, as well as almost all other uses of floating point constants in the RISC-V backend tests. Reviewed By: luismarques, asb Differential Revision: https://reviews.llvm.org/D79523
111 lines
3.0 KiB
LLVM
111 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f < %s \
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; RUN: | FileCheck --check-prefix=RV32F %s
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; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+f,+d < %s \
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; RUN: | FileCheck --check-prefix=RV32D %s
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; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+f < %s \
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; RUN: | FileCheck --check-prefix=RV64F %s
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; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+f,+d < %s \
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; RUN: | FileCheck --check-prefix=RV64D %s
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define float @f32_positive_zero(float *%pf) nounwind {
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; RV32F-LABEL: f32_positive_zero:
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; RV32F: # %bb.0:
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; RV32F-NEXT: fmv.w.x fa0, zero
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; RV32F-NEXT: ret
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;
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; RV32D-LABEL: f32_positive_zero:
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; RV32D: # %bb.0:
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; RV32D-NEXT: fmv.w.x fa0, zero
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; RV32D-NEXT: ret
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;
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; RV64F-LABEL: f32_positive_zero:
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; RV64F: # %bb.0:
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; RV64F-NEXT: fmv.w.x fa0, zero
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; RV64F-NEXT: ret
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;
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; RV64D-LABEL: f32_positive_zero:
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; RV64D: # %bb.0:
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; RV64D-NEXT: fmv.w.x fa0, zero
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; RV64D-NEXT: ret
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ret float 0.0
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}
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define float @f32_negative_zero(float *%pf) nounwind {
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; RV32F-LABEL: f32_negative_zero:
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; RV32F: # %bb.0:
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; RV32F-NEXT: lui a0, %hi(.LCPI1_0)
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; RV32F-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
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; RV32F-NEXT: ret
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;
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; RV32D-LABEL: f32_negative_zero:
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; RV32D: # %bb.0:
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; RV32D-NEXT: lui a0, %hi(.LCPI1_0)
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; RV32D-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
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; RV32D-NEXT: ret
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;
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; RV64F-LABEL: f32_negative_zero:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a0, %hi(.LCPI1_0)
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; RV64F-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
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; RV64F-NEXT: ret
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;
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; RV64D-LABEL: f32_negative_zero:
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; RV64D: # %bb.0:
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; RV64D-NEXT: lui a0, %hi(.LCPI1_0)
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; RV64D-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
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; RV64D-NEXT: ret
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ret float -0.0
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}
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define double @f64_positive_zero(double *%pd) nounwind {
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; RV32F-LABEL: f64_positive_zero:
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; RV32F: # %bb.0:
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; RV32F-NEXT: mv a0, zero
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; RV32F-NEXT: mv a1, zero
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; RV32F-NEXT: ret
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;
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; RV32D-LABEL: f64_positive_zero:
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; RV32D: # %bb.0:
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; RV32D-NEXT: fcvt.d.w fa0, zero
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; RV32D-NEXT: ret
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;
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; RV64F-LABEL: f64_positive_zero:
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; RV64F: # %bb.0:
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; RV64F-NEXT: mv a0, zero
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; RV64F-NEXT: ret
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;
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; RV64D-LABEL: f64_positive_zero:
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; RV64D: # %bb.0:
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; RV64D-NEXT: fmv.d.x fa0, zero
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; RV64D-NEXT: ret
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ret double 0.0
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}
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define double @f64_negative_zero(double *%pd) nounwind {
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; RV32F-LABEL: f64_negative_zero:
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; RV32F: # %bb.0:
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; RV32F-NEXT: lui a1, 524288
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; RV32F-NEXT: mv a0, zero
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; RV32F-NEXT: ret
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;
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; RV32D-LABEL: f64_negative_zero:
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; RV32D: # %bb.0:
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; RV32D-NEXT: lui a0, %hi(.LCPI3_0)
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; RV32D-NEXT: fld fa0, %lo(.LCPI3_0)(a0)
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; RV32D-NEXT: ret
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;
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; RV64F-LABEL: f64_negative_zero:
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; RV64F: # %bb.0:
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; RV64F-NEXT: addi a0, zero, -1
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; RV64F-NEXT: slli a0, a0, 63
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; RV64F-NEXT: ret
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;
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; RV64D-LABEL: f64_negative_zero:
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; RV64D: # %bb.0:
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; RV64D-NEXT: lui a0, %hi(.LCPI3_0)
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; RV64D-NEXT: fld fa0, %lo(.LCPI3_0)(a0)
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; RV64D-NEXT: ret
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ret double -0.0
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}
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