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a2254d3fcc
If we need to shift left anyway we might be able to take advantage of LUI implicitly shifting its immediate left by 12 to cover part of the shift. This allows us to use more bits of the LUI immediate to avoid an ADDI. isDesirableToCommuteWithShift now considers compressed instruction opportunities when deciding if commuting should be allowed. I believe this is the same or similar to one of the optimizations from D79492. Reviewed By: luismarques, arcbbb Differential Revision: https://reviews.llvm.org/D105417
33 lines
1.1 KiB
LLVM
33 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
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;
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; The test case check that RV64 could handle the stack adjustment offset exceed
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; 32-bit.
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define void @foo() nounwind {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi sp, sp, -2032
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; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
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; CHECK-NEXT: lui a0, 390625
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; CHECK-NEXT: slli a0, a0, 1
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; CHECK-NEXT: addi a0, a0, -2000
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; CHECK-NEXT: sub sp, sp, a0
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: call baz@plt
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; CHECK-NEXT: lui a0, 390625
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; CHECK-NEXT: slli a0, a0, 1
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; CHECK-NEXT: addi a0, a0, -2000
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 2032
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; CHECK-NEXT: ret
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entry:
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%w = alloca [100000000 x { fp128, fp128 }], align 16
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%arraydecay = getelementptr inbounds [100000000 x { fp128, fp128 }], [100000000 x { fp128, fp128 }]* %w, i64 0, i64 0
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call void @baz({ fp128, fp128 }* nonnull %arraydecay)
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ret void
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}
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declare void @baz({ fp128, fp128 }*)
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