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88feba99f6
This teaches DAG combine that shift amount operands for grev, gorc shfl, unshfl only read a few bits. This also teaches DAG combine that grevw, gorcw, shflw, unshflw, bcompressw, bdecompressw only consume the lower 32 bits of their inputs. In the future we can teach SimplifyDemandedBits to also propagate demanded bits of the output to the inputs in some cases.
110 lines
3.3 KiB
LLVM
110 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IB
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IBE
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declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
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define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind {
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; RV64IB-LABEL: bcompress32:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bcompressw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBE-LABEL: bcompress32:
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; RV64IBE: # %bb.0:
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; RV64IBE-NEXT: bcompressw a0, a0, a1
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; RV64IBE-NEXT: ret
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%tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
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ret i32 %tmp
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}
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define signext i32 @bcompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV64IB-LABEL: bcompress32_demandedbits:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: add a0, a0, a1
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; RV64IB-NEXT: add a1, a2, a3
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; RV64IB-NEXT: bcompressw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBE-LABEL: bcompress32_demandedbits:
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; RV64IBE: # %bb.0:
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; RV64IBE-NEXT: add a0, a0, a1
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; RV64IBE-NEXT: add a1, a2, a3
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; RV64IBE-NEXT: bcompressw a0, a0, a1
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; RV64IBE-NEXT: ret
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%e = add i32 %a, %b
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%f = add i32 %c, %d
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%tmp = call i32 @llvm.riscv.bcompress.i32(i32 %e, i32 %f)
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ret i32 %tmp
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}
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declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
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define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind {
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; RV64IB-LABEL: bdecompress32:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bdecompressw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBE-LABEL: bdecompress32:
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; RV64IBE: # %bb.0:
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; RV64IBE-NEXT: bdecompressw a0, a0, a1
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; RV64IBE-NEXT: ret
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%tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
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ret i32 %tmp
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}
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define signext i32 @bdecompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV64IB-LABEL: bdecompress32_demandedbits:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: add a0, a0, a1
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; RV64IB-NEXT: add a1, a2, a3
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; RV64IB-NEXT: bdecompressw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBE-LABEL: bdecompress32_demandedbits:
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; RV64IBE: # %bb.0:
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; RV64IBE-NEXT: add a0, a0, a1
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; RV64IBE-NEXT: add a1, a2, a3
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; RV64IBE-NEXT: bdecompressw a0, a0, a1
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; RV64IBE-NEXT: ret
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%e = add i32 %a, %b
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%f = add i32 %c, %d
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%tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %e, i32 %f)
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ret i32 %tmp
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}
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declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
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define i64 @bcompress64(i64 %a, i64 %b) nounwind {
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; RV64IB-LABEL: bcompress64:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bcompress a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBE-LABEL: bcompress64:
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; RV64IBE: # %bb.0:
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; RV64IBE-NEXT: bcompress a0, a0, a1
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; RV64IBE-NEXT: ret
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%tmp = call i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
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define i64 @bdecompress64(i64 %a, i64 %b) nounwind {
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; RV64IB-LABEL: bdecompress64:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bdecompress a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBE-LABEL: bdecompress64:
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; RV64IBE: # %bb.0:
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; RV64IBE-NEXT: bdecompress a0, a0, a1
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; RV64IBE-NEXT: ret
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%tmp = call i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
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ret i64 %tmp
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}
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