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a2254d3fcc
If we need to shift left anyway we might be able to take advantage of LUI implicitly shifting its immediate left by 12 to cover part of the shift. This allows us to use more bits of the LUI immediate to avoid an ADDI. isDesirableToCommuteWithShift now considers compressed instruction opportunities when deciding if commuting should be allowed. I believe this is the same or similar to one of the optimizations from D79492. Reviewed By: luismarques, arcbbb Differential Revision: https://reviews.llvm.org/D105417
286 lines
8.8 KiB
LLVM
286 lines
8.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
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define i32 @fold_urem_positive_odd(i32 %x) nounwind {
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; RV32I-LABEL: fold_urem_positive_odd:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: addi a1, zero, 95
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; RV32I-NEXT: call __umodsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: fold_urem_positive_odd:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 364242
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; RV32IM-NEXT: addi a1, a1, 777
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; RV32IM-NEXT: mulhu a1, a0, a1
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; RV32IM-NEXT: sub a2, a0, a1
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; RV32IM-NEXT: srli a2, a2, 1
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; RV32IM-NEXT: add a1, a2, a1
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; RV32IM-NEXT: srli a1, a1, 6
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; RV32IM-NEXT: addi a2, zero, 95
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: sub a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: fold_urem_positive_odd:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: addi a1, zero, 95
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; RV64I-NEXT: call __umoddi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: fold_urem_positive_odd:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: slli a1, a0, 32
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; RV64IM-NEXT: srli a1, a1, 32
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; RV64IM-NEXT: lui a2, 364242
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; RV64IM-NEXT: addiw a2, a2, 777
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: srli a1, a1, 32
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; RV64IM-NEXT: sub a2, a0, a1
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; RV64IM-NEXT: srliw a2, a2, 1
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; RV64IM-NEXT: add a1, a2, a1
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; RV64IM-NEXT: srli a1, a1, 6
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; RV64IM-NEXT: addi a2, zero, 95
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: subw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = urem i32 %x, 95
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ret i32 %1
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}
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define i32 @fold_urem_positive_even(i32 %x) nounwind {
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; RV32I-LABEL: fold_urem_positive_even:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: addi a1, zero, 1060
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; RV32I-NEXT: call __umodsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: fold_urem_positive_even:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 1012964
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; RV32IM-NEXT: addi a1, a1, -61
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; RV32IM-NEXT: mulhu a1, a0, a1
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; RV32IM-NEXT: srli a1, a1, 10
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; RV32IM-NEXT: addi a2, zero, 1060
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: sub a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: fold_urem_positive_even:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: addi a1, zero, 1060
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; RV64I-NEXT: call __umoddi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: fold_urem_positive_even:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: slli a1, a0, 32
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; RV64IM-NEXT: srli a1, a1, 32
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; RV64IM-NEXT: lui a2, 253241
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; RV64IM-NEXT: slli a2, a2, 2
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; RV64IM-NEXT: addi a2, a2, -61
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: srli a1, a1, 42
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; RV64IM-NEXT: addi a2, zero, 1060
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: subw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = urem i32 %x, 1060
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ret i32 %1
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}
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; Don't fold if we can combine urem with udiv.
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define i32 @combine_urem_udiv(i32 %x) nounwind {
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; RV32I-LABEL: combine_urem_udiv:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
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; RV32I-NEXT: mv s0, a0
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; RV32I-NEXT: addi a1, zero, 95
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; RV32I-NEXT: call __umodsi3@plt
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; RV32I-NEXT: mv s1, a0
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; RV32I-NEXT: addi a1, zero, 95
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; RV32I-NEXT: mv a0, s0
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; RV32I-NEXT: call __udivsi3@plt
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; RV32I-NEXT: add a0, s1, a0
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; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: combine_urem_udiv:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 364242
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; RV32IM-NEXT: addi a1, a1, 777
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; RV32IM-NEXT: mulhu a1, a0, a1
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; RV32IM-NEXT: sub a2, a0, a1
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; RV32IM-NEXT: srli a2, a2, 1
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; RV32IM-NEXT: add a1, a2, a1
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; RV32IM-NEXT: srli a1, a1, 6
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; RV32IM-NEXT: addi a2, zero, 95
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; RV32IM-NEXT: mul a2, a1, a2
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; RV32IM-NEXT: sub a0, a0, a2
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: combine_urem_udiv:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -32
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; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli s0, a0, 32
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; RV64I-NEXT: addi a1, zero, 95
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; RV64I-NEXT: mv a0, s0
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; RV64I-NEXT: call __umoddi3@plt
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; RV64I-NEXT: mv s1, a0
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; RV64I-NEXT: addi a1, zero, 95
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; RV64I-NEXT: mv a0, s0
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; RV64I-NEXT: call __udivdi3@plt
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; RV64I-NEXT: add a0, s1, a0
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; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: combine_urem_udiv:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: slli a1, a0, 32
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; RV64IM-NEXT: srli a1, a1, 32
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; RV64IM-NEXT: lui a2, 364242
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; RV64IM-NEXT: addiw a2, a2, 777
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: srli a1, a1, 32
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; RV64IM-NEXT: sub a2, a0, a1
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; RV64IM-NEXT: srliw a2, a2, 1
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; RV64IM-NEXT: add a1, a2, a1
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; RV64IM-NEXT: srli a1, a1, 6
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; RV64IM-NEXT: addi a2, zero, 95
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; RV64IM-NEXT: mul a2, a1, a2
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; RV64IM-NEXT: sub a0, a0, a2
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; RV64IM-NEXT: addw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = urem i32 %x, 95
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%2 = udiv i32 %x, 95
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%3 = add i32 %1, %2
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ret i32 %3
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}
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; Don't fold for divisors that are a power of two.
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define i32 @dont_fold_urem_power_of_two(i32 %x) nounwind {
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; CHECK-LABEL: dont_fold_urem_power_of_two:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 63
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; CHECK-NEXT: ret
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%1 = urem i32 %x, 64
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ret i32 %1
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}
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; Don't fold if the divisor is one.
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define i32 @dont_fold_urem_one(i32 %x) nounwind {
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; CHECK-LABEL: dont_fold_urem_one:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mv a0, zero
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; CHECK-NEXT: ret
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%1 = urem i32 %x, 1
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ret i32 %1
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}
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; Don't fold if the divisor is 2^32.
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define i32 @dont_fold_urem_i32_umax(i32 %x) nounwind {
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; CHECK-LABEL: dont_fold_urem_i32_umax:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ret
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%1 = urem i32 %x, 4294967296
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ret i32 %1
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}
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; Don't fold i64 urem
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define i64 @dont_fold_urem_i64(i64 %x) nounwind {
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; RV32I-LABEL: dont_fold_urem_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: addi a2, zero, 98
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; RV32I-NEXT: mv a3, zero
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; RV32I-NEXT: call __umoddi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: dont_fold_urem_i64:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -16
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; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IM-NEXT: addi a2, zero, 98
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; RV32IM-NEXT: mv a3, zero
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; RV32IM-NEXT: call __umoddi3@plt
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; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: dont_fold_urem_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: addi a1, zero, 98
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; RV64I-NEXT: call __umoddi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: dont_fold_urem_i64:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: srli a1, a0, 1
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; RV64IM-NEXT: lui a2, 2675
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; RV64IM-NEXT: addiw a2, a2, -251
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; RV64IM-NEXT: slli a2, a2, 13
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; RV64IM-NEXT: addi a2, a2, 1839
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; RV64IM-NEXT: slli a2, a2, 13
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; RV64IM-NEXT: addi a2, a2, 167
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; RV64IM-NEXT: slli a2, a2, 13
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; RV64IM-NEXT: addi a2, a2, 1505
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; RV64IM-NEXT: mulhu a1, a1, a2
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; RV64IM-NEXT: srli a1, a1, 4
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; RV64IM-NEXT: addi a2, zero, 98
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: sub a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = urem i64 %x, 98
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ret i64 %1
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}
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