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llvm-mirror/lib/Target/AMDGPU
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Nicolai Haehnle b68efce7c9 AMDGPU/SI: xnack_mask is always reserved on VI 
Summary:
Somehow, I first interpreted the docs as saying space for xnack_mask is only
reserved when XNACK is enabled via SH_MEM_CONFIG. I felt uneasy about this and
went back to actually test what is happening, and it turns out that xnack_mask
is always reserved at least on Tonga and Carrizo, in the sense that flat_scr
is always fixed below the SGPRs that are used to implement xnack_mask, whether
or not they are actually used.

I confirmed this by writing a shader using inline assembly to tease out the
aliasing between flat_scratch and regular SGPRs. For example, on Tonga, where
we fix the number of SGPRs to 80, s[74:75] aliases flat_scratch (so
xnack_mask is s[76:77] and vcc is s[78:79]).

This patch changes both the calculation of the total number of SGPRs and the
various register reservations to account for this.

It ought to be possible to use the gap left by xnack_mask when the feature
isn't used, but this patch doesn't try to do that. (Note that the same applies
to vcc.)

Note that previously, even before my earlier change in r256794, the SGPRs that
alias to xnack_mask could end up being used as well when flat_scr was unused
and the total number of SGPRs happened to fall on the right alignment
(e.g. highest regular SGPR being used s29 and VCC used would lead to number
of SGPRs being 32, where s28 and s29 alias with xnack_mask). So if there
were some conflict due to such aliasing, we should have noticed that already.

Reviewers: arsenm, tstellarAMD

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15898

llvm-svn: 257073
2016-01-07 17:10:20 +00:00
..
AsmParser AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI 2015-12-21 18:44:27 +00:00
InstPrinter Remove extra forward declarations and scrub includes for all in tree InstPrinters. NFC 2015-12-25 22:10:01 +00:00
MCTargetDesc AMDGPU/SI: Fix warning introduced by r255204 2015-12-10 03:10:46 +00:00
TargetInfo
Utils AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI 2015-12-21 18:44:27 +00:00
AMDGPU.h AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions 2015-12-15 20:55:55 +00:00
AMDGPU.td AMDGPU: add +xnack feature 2016-01-04 23:35:53 +00:00
AMDGPUAlwaysInlinePass.cpp AMDGPU: Minor cleanups to always inline pass 2015-07-13 19:08:36 +00:00
AMDGPUAnnotateKernelFeatures.cpp AMDGPU: Add llvm.amdgcn.dispatch.ptr intrinsic 2015-11-26 00:43:29 +00:00
AMDGPUAnnotateUniformValues.cpp AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions 2015-12-15 20:55:55 +00:00
AMDGPUAsmPrinter.cpp AMDGPU/SI: xnack_mask is always reserved on VI 2016-01-07 17:10:20 +00:00
AMDGPUAsmPrinter.h AMDGPU/SI: Emit constant arrays in the .text section 2015-12-10 02:13:01 +00:00
AMDGPUCallingConv.td
AMDGPUDiagnosticInfoUnsupported.cpp AMDGPU: Split DiagnosticInfoUnsupported into its own file 2015-10-21 22:37:46 +00:00
AMDGPUDiagnosticInfoUnsupported.h AMDGPU: Split DiagnosticInfoUnsupported into its own file 2015-10-21 22:37:46 +00:00
AMDGPUFrameLowering.cpp Remove redundant TargetFrameLowering::getFrameIndexOffset virtual 2015-08-15 02:32:35 +00:00
AMDGPUFrameLowering.h AMDGPU: Create emergency stack slots during frame lowering 2015-11-06 18:17:45 +00:00
AMDGPUInstrInfo.cpp Make a bunch of static arrays const. 2015-10-18 05:15:34 +00:00
AMDGPUInstrInfo.h AMDGPU: Make getNamedOperandIdx declaration readonly 2015-09-25 18:09:15 +00:00
AMDGPUInstrInfo.td AMDGPU: Use generic bitreverse intrinsic 2015-12-14 17:25:38 +00:00
AMDGPUInstructions.td AMDGPU/SI: Consolidate FLAT patterns 2016-01-05 02:26:37 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td AMDGPU: Switch barrier intrinsics to using convergent 2015-12-19 01:46:41 +00:00
AMDGPUISelDAGToDAG.cpp AMDGPU/SI: Use flat for global load/store when targeting HSA 2015-12-22 20:55:23 +00:00
AMDGPUISelLowering.cpp AMDGPU: Use generic bitreverse intrinsic 2015-12-14 17:25:38 +00:00
AMDGPUISelLowering.h AMDGPU: Use generic bitreverse intrinsic 2015-12-14 17:25:38 +00:00
AMDGPUMachineFunction.cpp AMDGPU/SI: Add getShaderType() function to Utils/ 2015-12-15 16:26:16 +00:00
AMDGPUMachineFunction.h AMDGPU/SI: Emit HSA kernels with symbol type STT_AMDGPU_HSA_KERNEL 2015-11-06 11:45:14 +00:00
AMDGPUMCInstLower.cpp AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI 2015-12-21 18:44:27 +00:00
AMDGPUMCInstLower.h
AMDGPUOpenCLImageTypeLoweringPass.cpp AMDGPU/SI: Remove assert from AMDGPUOpenCLImageTypeLowering pass 2015-10-01 21:16:05 +00:00
AMDGPUPromoteAlloca.cpp Revert "Change memcpy/memset/memmove to have dest and source alignments." 2015-11-19 05:56:52 +00:00
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h AMDGPU: Remove dead code 2015-09-19 06:41:10 +00:00
AMDGPURegisterInfo.td AMDGPU: Set SubRegIndex size and offset 2015-07-30 17:03:11 +00:00
AMDGPUSubtarget.cpp AMDGPU: add +xnack feature 2016-01-04 23:35:53 +00:00
AMDGPUSubtarget.h AMDGPU: add +xnack feature 2016-01-04 23:35:53 +00:00
AMDGPUTargetMachine.cpp AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions 2015-12-15 20:55:55 +00:00
AMDGPUTargetMachine.h AMDGPU/SI: Use .hsatext section instead of .text for HSA 2015-09-25 21:41:28 +00:00
AMDGPUTargetObjectFile.cpp AMDGPU/SI: Emit constant variables in the .hsatext section when targeting HSA 2015-12-15 22:39:36 +00:00
AMDGPUTargetObjectFile.h AMDGPU/SI: Emit constant arrays in the .text section 2015-12-10 02:13:01 +00:00
AMDGPUTargetTransformInfo.cpp AMDGPU: Fix getRegisterBitWidth for vectors 2015-12-24 05:14:55 +00:00
AMDGPUTargetTransformInfo.h AMDGPU: Override getCFInstrCost 2015-12-16 18:37:19 +00:00
AMDILCFGStructurizer.cpp Normalize MBB's successors' probabilities in several locations. 2015-12-13 09:26:17 +00:00
AMDKernelCodeT.h AMDGPU/SI: Update amd_kernel_code_t definition and add assembler support 2015-06-26 21:58:31 +00:00
CaymanInstructions.td AMDGPU: Add MEM_RAT STORE_TYPED. 2015-10-01 17:51:34 +00:00
CIInstructions.td AMDGPU/SI: Consolidate FLAT patterns 2016-01-05 02:26:37 +00:00
CMakeLists.txt AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions 2015-12-15 20:55:55 +00:00
EvergreenInstructions.td AMDGPU: Add MEM_RAT STORE_TYPED. 2015-10-01 17:51:34 +00:00
LLVMBuild.txt AMDGPU/SI: Add hsa code object directives 2015-06-26 21:15:07 +00:00
Makefile AMDGPU/SI: Add hsa code object directives 2015-06-26 21:15:07 +00:00
Processors.td AMDGPU: Add stony support 2015-11-13 17:06:32 +00:00
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp AMDGPU: Remove implicit ilist iterator conversions, NFC 2015-10-13 20:07:10 +00:00
R600Defines.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp Pass BranchProbability/BlockMass by value instead of const& as they are small. NFC. 2015-09-10 23:10:42 +00:00
R600InstrInfo.h Pass BranchProbability/BlockMass by value instead of const& as they are small. NFC. 2015-09-10 23:10:42 +00:00
R600Instructions.td Fix typos. 2015-09-12 01:17:08 +00:00
R600Intrinsics.td
R600ISelLowering.cpp AMDGPU: Add MEM_RAT STORE_TYPED. 2015-10-01 17:51:34 +00:00
R600ISelLowering.h Make TargetLowering::getPointerTy() taking DataLayout as an argument 2015-07-09 02:09:04 +00:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp AMDGPU: Remove implicit ilist iterator conversions, NFC 2015-10-13 20:07:10 +00:00
R600Packetizer.cpp [Packetizer] Add AliasAnalysis as a parameter to the packetizer 2015-12-14 20:35:13 +00:00
R600RegisterInfo.cpp
R600RegisterInfo.h AMDGPU: Remove dead code 2015-09-19 06:41:10 +00:00
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
R700Instructions.td
SIAnnotateControlFlow.cpp AMDGPU: Remove implicit ilist iterator conversions, NFC 2015-10-13 20:07:10 +00:00
SIDefines.h AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp 2015-10-06 15:57:53 +00:00
SIFixControlFlowLiveIntervals.cpp AMDGPU: Remove unused includes 2015-09-25 00:28:43 +00:00
SIFixSGPRCopies.cpp AMDGPU: Initialize SIFixSGPRCopies so -print-after works 2015-11-03 22:30:13 +00:00
SIFixSGPRLiveRanges.cpp AMDGPU: Remove implicit ilist iterator conversions, NFC 2015-10-13 20:07:10 +00:00
SIFoldOperands.cpp AMDGPU: Fix verifier error in SIFoldOperands 2015-10-21 22:37:50 +00:00
SIFrameLowering.cpp AMDGPU/SI: Do not move scratch resource register on Tonga & Iceland 2016-01-05 20:42:49 +00:00
SIFrameLowering.h AMDGPU: Remove SIPrepareScratchRegs 2015-11-30 21:15:53 +00:00
SIInsertWaits.cpp AMDGPU: Add MachineInstr overloads for instruction format tests 2015-10-20 04:35:43 +00:00
SIInstrFormats.td AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp 2015-10-06 15:57:53 +00:00
SIInstrInfo.cpp AMDGPU/SI: use S_MOV_B64 for larger copies in copyPhysReg 2015-12-19 01:36:26 +00:00
SIInstrInfo.h AMDGPU: Fix off-by-one in SIRegisterInfo::eliminateFrameIndex 2015-12-17 16:46:42 +00:00
SIInstrInfo.td AMDGPU/SI: Select non-uniform constant addrspace loads to flat instructions for HSA 2016-01-05 03:40:16 +00:00
SIInstructions.td AMDGPU: Remove redundant let mayLoad = 1 2016-01-05 04:50:28 +00:00
SIIntrinsics.td
SIISelLowering.cpp AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions 2015-12-15 20:55:55 +00:00
SIISelLowering.h AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions 2015-12-15 20:55:55 +00:00
SILoadStoreOptimizer.cpp AMDGPU/SI: Fix read2 merging into a super register. 2015-07-14 17:57:36 +00:00
SILowerControlFlow.cpp AMDGPU: Fix adding redundant m0 uses 2015-10-21 22:37:51 +00:00
SILowerI1Copies.cpp AMDGPU: Fix recomputing dominator tree unnecessarily 2015-09-25 17:21:28 +00:00
SIMachineFunctionInfo.cpp AMDGPU: Avoid assertions after SGPR spilling failed 2016-01-04 15:50:01 +00:00
SIMachineFunctionInfo.h AMDGPU: Rework how private buffer passed for HSA 2015-11-30 21:16:03 +00:00
SIRegisterInfo.cpp AMDGPU/SI: xnack_mask is always reserved on VI 2016-01-07 17:10:20 +00:00
SIRegisterInfo.h AMDGPU: Optimize VOP2 operand legalization 2015-12-01 19:57:17 +00:00
SIRegisterInfo.td AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI 2015-12-21 18:44:27 +00:00
SISchedule.td AMDGPU: Improve accuracy of instruction rates for VOPC 2015-09-25 16:58:25 +00:00
SIShrinkInstructions.cpp AMDGPU: Add MachineInstr overloads for instruction format tests 2015-10-20 04:35:43 +00:00
SITypeRewriter.cpp AMDGPU/SI: Fix crash when inline assembly is used in a graphics shader 2016-01-06 22:01:04 +00:00
VIInstrFormats.td
VIInstructions.td AMDGPU/SI: Move VI SMEM pattern back into VIInstructions.td 2016-01-04 20:23:10 +00:00