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llvm-mirror/test/CodeGen
2018-09-10 21:49:01 +00:00
..
AArch64 [AArch64] Support reserving x1-7 registers. 2018-09-07 20:58:57 +00:00
AMDGPU [AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32. 2018-09-10 16:42:49 +00:00
ARC
ARM ARM: fix Thumb2 CodeGen for ldrex with folded frame-index. 2018-09-07 09:21:25 +00:00
AVR [AVR] Redefine the 'LSL' instruction as an alias of 'ADD' 2018-09-01 12:23:00 +00:00
BPF
Generic
Hexagon Add support for getRegisterByName. 2018-09-07 13:36:21 +00:00
Inputs
Lanai
Mips [MIPS GlobalISel] Select icmp 2018-09-10 15:56:52 +00:00
MIR AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
MSP430
Nios2
NVPTX
PowerPC [PowerPC] Combine ADD to ADDZE 2018-09-07 07:56:05 +00:00
RISCV
SPARC
SystemZ
Thumb
Thumb2
WebAssembly [WebAssembly] v8x16.shuffle 2018-09-07 21:54:46 +00:00
WinCFGuard
WinEH
X86 [X89] Explicitly enable aes in aes-schedule.ll to fix failures after r341861. 2018-09-10 21:49:01 +00:00
XCore