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7cd663b80c
Generally, the ISEL is expanded into if-then-else sequence, in some cases (like when the destination register is the same with the true or false value register), it may just be expanded into just the if or else sequence. llvm-svn: 292154
57 lines
1.7 KiB
LLVM
57 lines
1.7 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind readnone
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define signext i32 @crbitsoff(i32 signext %v1, i32 signext %v2) #0 {
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entry:
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%tobool = icmp ne i32 %v1, 0
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%lnot = icmp eq i32 %v2, 0
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%and3 = and i1 %tobool, %lnot
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%and = zext i1 %and3 to i32
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ret i32 %and
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; CHECK-LABEL: @crbitsoff
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; CHECK-NO-ISEL-LABEL: @crbitsoff
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; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0
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; CHECK-DAG: li [[REG2:[0-9]+]], 1
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; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
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; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]]
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; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
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; CHECK-NO-ISEL: ori 4, 5, 0
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; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
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; CHECK-NO-ISEL: [[TRUE]]
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; CHECK-NO-ISEL-NEXT: addi 4, 0, 0
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; CHECK: and 3, [[REG4]], [[REG3]]
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; CHECK: blr
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}
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define signext i32 @crbitson(i32 signext %v1, i32 signext %v2) #1 {
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entry:
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%tobool = icmp ne i32 %v1, 0
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%lnot = icmp eq i32 %v2, 0
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%and3 = and i1 %tobool, %lnot
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%and = zext i1 %and3 to i32
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ret i32 %and
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; CHECK-LABEL: @crbitson
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; CHECK-NO-ISEL-LABEL: @crbitson
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; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0
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; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0
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; CHECK-DAG: li [[REG2:[0-9]+]], 1
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; CHECK-DAG: crorc [[REG3:[0-9]+]],
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; CHECK: isel 3, 0, [[REG2]], [[REG3]]
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; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
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; CHECK-NO-ISEL-NEXT: blr
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; CHECK-NO-ISEL: [[TRUE]]
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; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
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; CHECK-NO-ISEL-NEXT: blr
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; CHECK: blr
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}
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attributes #0 = { nounwind readnone "target-features"="-crbits" }
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attributes #1 = { nounwind readnone }
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