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llvm-mirror/test/CodeGen/ARM/setcc-sentinals.ll
Tim Northover eb7a86ed88 ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.

TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.

llvm-svn: 188995
2013-08-22 09:57:11 +00:00

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LLVM

; RUN: llc < %s -mcpu=cortex-a8 -march=arm -asm-verbose=false | FileCheck %s
define zeroext i1 @test0(i32 %x) nounwind {
; CHECK-LABEL: test0:
; CHECK-NEXT: add [[REG:(r[0-9]+)|(lr)]], r0, #1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: cmp [[REG]], #1
; CHECK-NEXT: movwhi r0, #1
; CHECK-NEXT: bx lr
%cmp1 = icmp ne i32 %x, -1
%not.cmp = icmp ne i32 %x, 0
%.cmp1 = and i1 %cmp1, %not.cmp
ret i1 %.cmp1
}