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06563fec33
We do use a very small set of physical registers, so account for them in the virtual register encoding between MachineInstr and MC llvm-svn: 187799
19 lines
763 B
LLVM
19 lines
763 B
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
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; Ensure we access the local stack properly
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; PTX32: mov.u32 %r{{[0-9]+}}, __local_depot{{[0-9]+}};
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; PTX32: cvta.local.u32 %SP, %r{{[0-9]+}};
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; PTX32: ld.param.u32 %r{{[0-9]+}}, [foo_param_0];
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; PTX32: st.u32 [%SP+0], %r{{[0-9]+}};
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; PTX64: mov.u64 %rl{{[0-9]+}}, __local_depot{{[0-9]+}};
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; PTX64: cvta.local.u64 %SP, %rl{{[0-9]+}};
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; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo_param_0];
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; PTX64: st.u32 [%SP+0], %r{{[0-9]+}};
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define void @foo(i32 %a) {
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%local = alloca i32, align 4
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store i32 %a, i32* %local
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ret void
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}
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