mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 03:53:04 +02:00
b7fb5f7be7
Some ISA's such as microMIPS32(R6) have instructions which are near identical for code generation purposes, e.g. xor and xor16. These instructions take the same value types for operands and return values, have the same instruction predicates and map to the same ISD opcode. (These instructions do differ by register classes.) In such cases, the FastISel generator rejects the instruction definition. This patch borrows the 'FastIselShouldIgnore' bit from rL129692 and enables applying it to an instruction definition. Reviewers: mcrosier Differential Revision: https://reviews.llvm.org/D46953 llvm-svn: 332983 |
||
|---|---|---|
| .. | ||
| GlobalISel | ||
| CodeGenCWrappers.h | ||
| GenericOpcodes.td | ||
| Target.td | ||
| TargetCallingConv.td | ||
| TargetIntrinsicInfo.h | ||
| TargetItinerary.td | ||
| TargetLoweringObjectFile.h | ||
| TargetMachine.h | ||
| TargetOptions.h | ||
| TargetSchedule.td | ||
| TargetSelectionDAG.td | ||