mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 12:12:47 +01:00
840095b1e1
This adds a G_ASSERT_SEXT opcode, similar to G_ASSERT_ZEXT. This instruction signifies that an operation was already sign extended from a smaller type. This is useful for functions with sign-extended parameters. E.g. ``` define void @foo(i16 signext %x) { ... } ``` This adds verifier, regbankselect, and instruction selection support for G_ASSERT_SEXT equivalent to G_ASSERT_ZEXT. Differential Revision: https://reviews.llvm.org/D96890
43 lines
1.8 KiB
YAML
43 lines
1.8 KiB
YAML
# REQUIRES: aarch64-registered-target
|
|
# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
|
|
|
|
name: test
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0, $w0
|
|
%0:_(s64) = COPY $x0
|
|
%1:_(<4 x s16>) = COPY $x0
|
|
%2:_(s32) = COPY $w0
|
|
|
|
; CHECK: *** Bad machine code: G_ASSERT_SEXT expects an immediate operand #2 ***
|
|
; CHECK: instruction: %assert_sext_1:_(s64) = G_ASSERT_SEXT
|
|
%assert_sext_1:_(s64) = G_ASSERT_SEXT %0, %0
|
|
|
|
; CHECK: *** Bad machine code: G_ASSERT_SEXT expects an immediate operand #2 ***
|
|
; CHECK: instruction: %assert_sext_2:_(s64) = G_ASSERT_SEXT
|
|
%assert_sext_2:_(s64) = G_ASSERT_SEXT %0, i8 8
|
|
|
|
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
|
|
; CHECK: instruction: %assert_sext_3:_(<2 x s32>) = G_ASSERT_SEXT
|
|
%assert_sext_3:_(<2 x s32>) = G_ASSERT_SEXT %0, 8
|
|
|
|
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
|
|
; CHECK: instruction: %assert_sext_4:_(<2 x s32>) = G_ASSERT_SEXT
|
|
%assert_sext_4:_(<2 x s32>) = G_ASSERT_SEXT %1, 8
|
|
|
|
; CHECK: *** Bad machine code: G_ASSERT_SEXT size must be >= 1 ***
|
|
; CHECK: instruction: %assert_sext_5:_(s64) = G_ASSERT_SEXT
|
|
%assert_sext_5:_(s64) = G_ASSERT_SEXT %0, 0
|
|
|
|
; CHECK: *** Bad machine code: G_ASSERT_SEXT size must be less than source bit width ***
|
|
; CHECK: instruction: %assert_sext_6:_(s64) = G_ASSERT_SEXT
|
|
%assert_sext_6:_(s64) = G_ASSERT_SEXT %0, 128
|
|
|
|
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
|
|
; CHECK: instruction: %assert_sext_7:_(s64) = G_ASSERT_SEXT %2:_, 8
|
|
%assert_sext_7:_(s64) = G_ASSERT_SEXT %2, 8
|
|
|
|
; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***
|
|
; CHECK: instruction: %assert_sext_8:_(s64) = G_ASSERT_SEXT $x0, 8
|
|
%assert_sext_8:_(s64) = G_ASSERT_SEXT $x0, 8
|