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generic-vreg-undef-use.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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live-ins-01.mir
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live-ins-02.mir
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live-ins-03.mir
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test_copy_mismatch_types.mir
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test_copy_physregs_x86.mir
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GlobalISel: Relax verification of physical register copy types
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2021-04-28 08:45:41 -04:00 |
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test_copy.mir
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test_g_add.mir
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test_g_addrspacecast.mir
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test_g_assert_sext_register_bank_class.mir
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[GlobalISel] Add G_ASSERT_SEXT
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2021-02-17 13:10:34 -08:00 |
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test_g_assert_sext.mir
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[GlobalISel] Add G_ASSERT_SEXT
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2021-02-17 13:10:34 -08:00 |
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test_g_assert_zext_register_bank_class.mir
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test_g_assert_zext.mir
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[GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT
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2021-02-12 21:33:27 +00:00 |
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test_g_bitcast.mir
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test_g_brindirect_is_indirect_branch.mir
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test_g_brjt_is_indirect_branch.mir
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test_g_brjt.mir
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test_g_build_vector_trunc.mir
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test_g_build_vector.mir
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test_g_bzero.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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test_g_concat_vectors.mir
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GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sources
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2021-03-01 09:10:36 -05:00 |
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test_g_constant.mir
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test_g_dyn_stackalloc.mir
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test_g_extract.mir
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test_g_fcmp.mir
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test_g_fconstant.mir
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test_g_icmp.mir
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test_g_insert.mir
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test_g_intrinsic_w_side_effects.mir
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test_g_intrinsic.mir
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test_g_inttoptr.mir
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test_g_jump_table.mir
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test_g_load.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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test_g_memcpy_inline.mir
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[GISel] Support llvm.memcpy.inline
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2021-06-30 12:39:05 -07:00 |
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test_g_memcpy.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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test_g_memmove.mir
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[GISel] Support llvm.memcpy.inline
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2021-06-30 12:39:05 -07:00 |
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test_g_memset.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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test_g_merge_values.mir
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test_g_phi.mir
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test_g_ptr_add.mir
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test_g_ptrmask.mir
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test_g_ptrtoint.mir
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test_g_rotr_rotl.mir
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[GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates.
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2021-03-25 17:23:30 -07:00 |
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test_g_select.mir
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test_g_sext_inreg.mir
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[GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT
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2021-02-12 21:33:27 +00:00 |
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test_g_sextload.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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test_g_shuffle_vector.mir
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test_g_store.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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test_g_trunc.mir
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test_g_ubfx_sbfx.mir
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Add missing -march to runline in llvm/test/MachineVerifier/test_g_ubfx_sbfx.mir
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2021-03-24 11:23:08 -07:00 |
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test_g_zextload.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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test_insert_subreg.mir
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[MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregs
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2021-07-21 08:47:17 -07:00 |
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test_phis_precede_nonphis.mir
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test_vector_reductions.mir
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verifier-generic-extend-truncate.mir
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verifier-generic-types-1.mir
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verifier-generic-types-2.mir
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verifier-implicit-virtreg-invalid-physreg-liveness.mir
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verifier-phi-fail0.mir
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verifier-phi.mir
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verifier-pseudo-terminators.mir
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verifier-statepoint.mir
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verify-regbankselected.mir
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verify-regops.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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verify-selected.mir
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