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AsmParser
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[RISCV] Implement pseudo instructions for load/store from a symbol address.
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2019-02-20 03:31:32 +00:00 |
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Disassembler
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[RISCV] Replace incorrect use of sizeof with array_lengthof
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2019-03-13 09:22:57 +00:00 |
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InstPrinter
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MCTargetDesc
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[RISCV][MC] Find matching pcrel_hi fixup in more cases.
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2019-03-12 18:14:16 +00:00 |
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TargetInfo
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Utils
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[RISCV] Support -target-abi at the MC layer and for codegen
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2019-03-09 09:28:06 +00:00 |
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CMakeLists.txt
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LLVMBuild.txt
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RISCV.h
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RISCV.td
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RISCVAsmPrinter.cpp
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RISCVCallingConv.td
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[RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor RISCVRegisterInfo refactoring
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2019-03-14 08:28:48 +00:00 |
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RISCVExpandPseudoInsts.cpp
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RISCVFrameLowering.cpp
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RISCVFrameLowering.h
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RISCVInstrFormats.td
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[RISCV] Implement pseudo instructions for load/store from a symbol address.
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2019-02-20 03:31:32 +00:00 |
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RISCVInstrFormatsC.td
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RISCVInstrInfo.cpp
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[RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()
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2019-03-11 20:43:29 +00:00 |
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RISCVInstrInfo.h
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RISCVInstrInfo.td
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[RISCV] Add implied zero offset load/store alias patterns
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2019-02-21 14:09:34 +00:00 |
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RISCVInstrInfoA.td
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RISCVInstrInfoC.td
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[RISCV] Add implied zero offset load/store alias patterns
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2019-02-21 14:09:34 +00:00 |
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RISCVInstrInfoD.td
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[RISCV] Add implied zero offset load/store alias patterns
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2019-02-21 14:09:34 +00:00 |
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RISCVInstrInfoF.td
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[RISCV] Add implied zero offset load/store alias patterns
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2019-02-21 14:09:34 +00:00 |
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RISCVInstrInfoM.td
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RISCVISelDAGToDAG.cpp
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RISCVISelLowering.cpp
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[RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()
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2019-03-11 20:43:29 +00:00 |
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RISCVISelLowering.h
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[RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A
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2019-03-11 21:41:22 +00:00 |
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RISCVMachineFunctionInfo.h
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RISCVMCInstLower.cpp
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RISCVMergeBaseOffset.cpp
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RISCVRegisterInfo.cpp
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[RISCV] Fix rL356123
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2019-03-14 08:31:35 +00:00 |
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RISCVRegisterInfo.h
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RISCVRegisterInfo.td
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[RISCV] Allow fp as an alias of s0
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2019-03-11 21:35:26 +00:00 |
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RISCVSubtarget.cpp
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[RISCV] Support -target-abi at the MC layer and for codegen
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2019-03-09 09:28:06 +00:00 |
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RISCVSubtarget.h
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[RISCV] Support -target-abi at the MC layer and for codegen
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2019-03-09 09:28:06 +00:00 |
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RISCVSystemOperands.td
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[RISCV] Allow access to FP CSRs without F extension
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2019-03-08 23:01:08 +00:00 |
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RISCVTargetMachine.cpp
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[RISCV] Support -target-abi at the MC layer and for codegen
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2019-03-09 09:28:06 +00:00 |
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RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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