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Currently when the target is big-endian vmov.i64 reverses the order of the two words of the vector. This is correct only when the underlying element type is 32-bit, as actually what it should be doing is considering it a vector of the underlying type and reversing the elements of that. Differential Revision: https://reviews.llvm.org/D76515
89 lines
2.5 KiB
LLVM
89 lines
2.5 KiB
LLVM
; RUN: llc < %s -mtriple armv7-eabi -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE
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; RUN: llc < %s -mtriple armebv7-eabi -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
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; CHECK-LABEL: vmov_i8
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; CHECK-LE: vmov.i64 d0, #0xff00000000000000{{$}}
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; CHECK-BE: vmov.i64 d0, #0xff{{$}}
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; CHECK-NEXT: bx lr
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define arm_aapcs_vfpcc <8 x i8> @vmov_i8() {
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ret <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 -1>
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}
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; CHECK-LABEL: vmov_i16_a:
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; CHECK-LE: vmov.i64 d0, #0xffff000000000000{{$}}
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; CHECK-BE: vmov.i64 d0, #0xffff{{$}}
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; CHECK-NEXT: bx lr
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define arm_aapcs_vfpcc <4 x i16> @vmov_i16_a() {
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ret <4 x i16> <i16 0, i16 0, i16 0, i16 -1>
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}
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; CHECK-LABEL: vmov_i16_b:
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; CHECK-LE: vmov.i64 d0, #0xff000000000000{{$}}
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; CHECK-BE: vmov.i64 d0, #0xff{{$}}
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; CHECK-NEXT: bx lr
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define arm_aapcs_vfpcc <4 x i16> @vmov_i16_b() {
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ret <4 x i16> <i16 0, i16 0, i16 0, i16 255>
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}
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; CHECK-LABEL: vmov_i16_c:
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; CHECK-LE: vmov.i64 d0, #0xff00000000000000{{$}}
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; CHECK-BE: vmov.i64 d0, #0xff00{{$}}
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; CHECK-NEXT: bx lr
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define arm_aapcs_vfpcc <4 x i16> @vmov_i16_c() {
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ret <4 x i16> <i16 0, i16 0, i16 0, i16 65280>
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}
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; CHECK-LABEL: vmov_i32_a:
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; CHECK-LE: vmov.i64 d0, #0xffffffff00000000{{$}}
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; CHECK-BE: vmov.i64 d0, #0xffffffff{{$}}
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; CHECK-NEXT: bx lr
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define arm_aapcs_vfpcc <2 x i32> @vmov_i32_a() {
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ret <2 x i32> <i32 0, i32 -1>
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}
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; CHECK-LABEL: vmov_i32_b:
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; CHECK-LE: vmov.i64 d0, #0xff00000000{{$}}
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; CHECK-BE: vmov.i64 d0, #0xff{{$}}
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; CHECK-NEXT: bx lr
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define arm_aapcs_vfpcc <2 x i32> @vmov_i32_b() {
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ret <2 x i32> <i32 0, i32 255>
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}
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; CHECK-LABEL: vmov_i32_c:
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; CHECK-LE: vmov.i64 d0, #0xff0000000000{{$}}
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; CHECK-BE: vmov.i64 d0, #0xff00{{$}}
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; CHECK-NEXT: bx lr
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define arm_aapcs_vfpcc <2 x i32> @vmov_i32_c() {
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ret <2 x i32> <i32 0, i32 65280>
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}
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; CHECK-LABEL: vmov_i32_d:
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; CHECK-LE: vmov.i64 d0, #0xff000000000000{{$}}
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; CHECK-BE: vmov.i64 d0, #0xff0000{{$}}
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; CHECK-NEXT: bx lr
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define arm_aapcs_vfpcc <2 x i32> @vmov_i32_d() {
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ret <2 x i32> <i32 0, i32 16711680>
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}
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; CHECK-LABEL: vmov_i32_e:
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; CHECK-LE: vmov.i64 d0, #0xff00000000000000{{$}}
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; CHECK-BE: vmov.i64 d0, #0xff000000{{$}}
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; CHECK-NEXT: bx lr
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define arm_aapcs_vfpcc <2 x i32> @vmov_i32_e() {
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ret <2 x i32> <i32 0, i32 4278190080>
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}
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; CHECK-LABEL: vmov_i64_a:
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; CHECK: vmov.i8 d0, #0xff{{$}}
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; CHECK-NEXT: bx lr
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define arm_aapcs_vfpcc <1 x i64> @vmov_i64_a() {
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ret <1 x i64> <i64 -1>
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}
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; CHECK-LABEL: vmov_i64_b:
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; CHECK: vmov.i64 d0, #0xffff00ff0000ff{{$}}
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; CHECK-NEXT: bx lr
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define arm_aapcs_vfpcc <1 x i64> @vmov_i64_b() {
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ret <1 x i64> <i64 72056498804490495>
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}
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