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7dcf1654f8
Based ontop of D104598, which is a NFCI-ish refactoring. Here, a restriction, that only empty blocks can be merged, is lifted. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D104597
32 lines
839 B
LLVM
32 lines
839 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8
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; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s -check-prefix=SWIFT
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define i32 @t1(i32 %a, i32 %b) {
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; A8-LABEL: t1:
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; A8: @ %bb.0: @ %common.ret
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; A8-NEXT: mov r2, #1
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; A8-NEXT: cmp r0, #0
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; A8-NEXT: mvneq r2, #0
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; A8-NEXT: add r0, r1, r2
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; A8-NEXT: bx lr
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;
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; SWIFT-LABEL: t1:
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; SWIFT: @ %bb.0: @ %common.ret
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; SWIFT-NEXT: mov r2, #1
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; SWIFT-NEXT: cmp r0, #0
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; SWIFT-NEXT: mvneq r2, #0
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; SWIFT-NEXT: add r0, r1, r2
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; SWIFT-NEXT: bx lr
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%tmp2 = icmp eq i32 %a, 0
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br i1 %tmp2, label %cond_false, label %cond_true
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cond_true:
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%tmp5 = add i32 %b, 1
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ret i32 %tmp5
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cond_false:
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%tmp7 = add i32 %b, -1
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ret i32 %tmp7
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}
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