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0a7fe2ac65
For now, we didn't set the default operation action for SIGN_EXTEND_INREG for vector type, which is 0 by default, that is legal. However, most target didn't have native instructions to support this opcode. It should be set as expand by default, as what we did for ANY_EXTEND_VECTOR_INREG. Differential Revision: https://reviews.llvm.org/D70000
18 lines
611 B
LLVM
18 lines
611 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=armv8 | FileCheck %s
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define <4 x i32> @test(<4 x i32> %m) {
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; CHECK-LABEL: test:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov d17, r2, r3
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; CHECK-NEXT: vmov d16, r0, r1
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; CHECK-NEXT: vshl.i32 q8, q8, #24
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; CHECK-NEXT: vshr.s32 q8, q8, #24
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: bx lr
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entry:
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%shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>
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%shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
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ret <4 x i32> %shr
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}
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