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https://github.com/RPCS3/llvm-mirror.git
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6e066a74ee
Same as a9b6440edd, use zanyext to treat any_extends as zero extends during lowering to create addw/addl/subw/subl nodes. Differential Revision: https://reviews.llvm.org/D93835
362 lines
10 KiB
LLVM
362 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
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define <8 x i8> @vsubi8(<8 x i8> %A, <8 x i8> %B) {
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; CHECK-LABEL: vsubi8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsub.i8 d0, d0, d1
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; CHECK-NEXT: bx lr
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%tmp3 = sub <8 x i8> %A, %B
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vsubi16(<4 x i16> %A, <4 x i16> %B) {
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; CHECK-LABEL: vsubi16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsub.i16 d0, d0, d1
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; CHECK-NEXT: bx lr
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%tmp3 = sub <4 x i16> %A, %B
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vsubi32(<2 x i32> %A, <2 x i32> %B) {
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; CHECK-LABEL: vsubi32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsub.i32 d0, d0, d1
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; CHECK-NEXT: bx lr
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%tmp3 = sub <2 x i32> %A, %B
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vsubi64(<1 x i64> %A, <1 x i64> %B) {
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; CHECK-LABEL: vsubi64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsub.i64 d0, d0, d1
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; CHECK-NEXT: bx lr
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%tmp3 = sub <1 x i64> %A, %B
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ret <1 x i64> %tmp3
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}
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define <2 x float> @vsubf32(<2 x float> %A, <2 x float> %B) {
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; CHECK-LABEL: vsubf32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsub.f32 d0, d0, d1
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; CHECK-NEXT: bx lr
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%tmp3 = fsub <2 x float> %A, %B
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ret <2 x float> %tmp3
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}
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define <16 x i8> @vsubQi8(<16 x i8> %A, <16 x i8> %B) {
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; CHECK-LABEL: vsubQi8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsub.i8 q0, q0, q1
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; CHECK-NEXT: bx lr
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%tmp3 = sub <16 x i8> %A, %B
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vsubQi16(<8 x i16> %A, <8 x i16> %B) {
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; CHECK-LABEL: vsubQi16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsub.i16 q0, q0, q1
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; CHECK-NEXT: bx lr
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%tmp3 = sub <8 x i16> %A, %B
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vsubQi32(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: vsubQi32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsub.i32 q0, q0, q1
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; CHECK-NEXT: bx lr
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%tmp3 = sub <4 x i32> %A, %B
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vsubQi64(<2 x i64> %A, <2 x i64> %B) {
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; CHECK-LABEL: vsubQi64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsub.i64 q0, q0, q1
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; CHECK-NEXT: bx lr
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%tmp3 = sub <2 x i64> %A, %B
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ret <2 x i64> %tmp3
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}
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define <4 x float> @vsubQf32(<4 x float> %A, <4 x float> %B) {
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; CHECK-LABEL: vsubQf32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsub.f32 q0, q0, q1
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; CHECK-NEXT: bx lr
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%tmp3 = fsub <4 x float> %A, %B
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ret <4 x float> %tmp3
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}
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define <8 x i8> @vrsubhni16(<8 x i16> %A, <8 x i16> %B) {
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; CHECK-LABEL: vrsubhni16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vrsubhn.i16 d0, q0, q1
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; CHECK-NEXT: bx lr
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%tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %A, <8 x i16> %B)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vrsubhni32(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: vrsubhni32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vrsubhn.i32 d0, q0, q1
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; CHECK-NEXT: bx lr
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%tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %A, <4 x i32> %B)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vrsubhni64(<2 x i64> %A, <2 x i64> %B) {
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; CHECK-LABEL: vrsubhni64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vrsubhn.i64 d0, q0, q1
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; CHECK-NEXT: bx lr
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%tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %A, <2 x i64> %B)
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ret <2 x i32> %tmp3
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}
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declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) readnone
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declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) readnone
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declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) readnone
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define <8 x i8> @vsubhni16_natural(<8 x i16> %A, <8 x i16> %B) {
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; CHECK-LABEL: vsubhni16_natural:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubhn.i16 d0, q0, q1
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; CHECK-NEXT: bx lr
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%sum = sub <8 x i16> %A, %B
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%shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%trunc = trunc <8 x i16> %shift to <8 x i8>
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ret <8 x i8> %trunc
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}
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define <4 x i16> @vsubhni32_natural(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: vsubhni32_natural:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubhn.i32 d0, q0, q1
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; CHECK-NEXT: bx lr
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%sum = sub <4 x i32> %A, %B
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%shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
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%trunc = trunc <4 x i32> %shift to <4 x i16>
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ret <4 x i16> %trunc
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}
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define <2 x i32> @vsubhni64_natural(<2 x i64> %A, <2 x i64> %B) {
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; CHECK-LABEL: vsubhni64_natural:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubhn.i64 d0, q0, q1
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; CHECK-NEXT: bx lr
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%sum = sub <2 x i64> %A, %B
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%shift = lshr <2 x i64> %sum, <i64 32, i64 32>
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%trunc = trunc <2 x i64> %shift to <2 x i32>
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ret <2 x i32> %trunc
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}
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define <8 x i16> @vsubls8(<8 x i8> %A, <8 x i8> %B) {
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; CHECK-LABEL: vsubls8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubl.s8 q0, d0, d1
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; CHECK-NEXT: bx lr
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%tmp3 = sext <8 x i8> %A to <8 x i16>
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%tmp4 = sext <8 x i8> %B to <8 x i16>
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%tmp5 = sub <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vsubls16(<4 x i16> %A, <4 x i16> %B) {
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; CHECK-LABEL: vsubls16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubl.s16 q0, d0, d1
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; CHECK-NEXT: bx lr
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%tmp3 = sext <4 x i16> %A to <4 x i32>
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%tmp4 = sext <4 x i16> %B to <4 x i32>
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%tmp5 = sub <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <2 x i64> @vsubls32(<2 x i32> %A, <2 x i32> %B) {
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; CHECK-LABEL: vsubls32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubl.s32 q0, d0, d1
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; CHECK-NEXT: bx lr
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%tmp3 = sext <2 x i32> %A to <2 x i64>
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%tmp4 = sext <2 x i32> %B to <2 x i64>
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%tmp5 = sub <2 x i64> %tmp3, %tmp4
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ret <2 x i64> %tmp5
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}
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define <8 x i16> @vsublu8(<8 x i8> %A, <8 x i8> %B) {
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; CHECK-LABEL: vsublu8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubl.u8 q0, d0, d1
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; CHECK-NEXT: bx lr
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%tmp3 = zext <8 x i8> %A to <8 x i16>
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%tmp4 = zext <8 x i8> %B to <8 x i16>
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%tmp5 = sub <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vsublu16(<4 x i16> %A, <4 x i16> %B) {
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; CHECK-LABEL: vsublu16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubl.u16 q0, d0, d1
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; CHECK-NEXT: bx lr
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%tmp3 = zext <4 x i16> %A to <4 x i32>
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%tmp4 = zext <4 x i16> %B to <4 x i32>
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%tmp5 = sub <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <2 x i64> @vsublu32(<2 x i32> %A, <2 x i32> %B) {
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; CHECK-LABEL: vsublu32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubl.u32 q0, d0, d1
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; CHECK-NEXT: bx lr
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%tmp3 = zext <2 x i32> %A to <2 x i64>
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%tmp4 = zext <2 x i32> %B to <2 x i64>
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%tmp5 = sub <2 x i64> %tmp3, %tmp4
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ret <2 x i64> %tmp5
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}
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define <8 x i16> @vsubla8(<8 x i8> %A, <8 x i8> %B) {
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; CHECK-LABEL: vsubla8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubl.u8 q0, d0, d1
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; CHECK-NEXT: vbic.i16 q0, #0xff00
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; CHECK-NEXT: bx lr
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%tmp3 = zext <8 x i8> %A to <8 x i16>
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%tmp4 = zext <8 x i8> %B to <8 x i16>
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%tmp5 = sub <8 x i16> %tmp3, %tmp4
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%and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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ret <8 x i16> %and
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}
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define <4 x i32> @vsubla16(<4 x i16> %A, <4 x i16> %B) {
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; CHECK-LABEL: vsubla16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q8, #0xffff
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; CHECK-NEXT: vsubl.u16 q9, d0, d1
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; CHECK-NEXT: vand q0, q9, q8
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; CHECK-NEXT: bx lr
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%tmp3 = zext <4 x i16> %A to <4 x i32>
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%tmp4 = zext <4 x i16> %B to <4 x i32>
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%tmp5 = sub <4 x i32> %tmp3, %tmp4
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%and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
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ret <4 x i32> %and
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}
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define <2 x i64> @vsubla32(<2 x i32> %A, <2 x i32> %B) {
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; CHECK-LABEL: vsubla32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i64 q8, #0xffffffff
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; CHECK-NEXT: vsubl.u32 q9, d0, d1
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; CHECK-NEXT: vand q0, q9, q8
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; CHECK-NEXT: bx lr
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%tmp3 = zext <2 x i32> %A to <2 x i64>
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%tmp4 = zext <2 x i32> %B to <2 x i64>
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%tmp5 = sub <2 x i64> %tmp3, %tmp4
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%and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>
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ret <2 x i64> %and
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}
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define <8 x i16> @vsubws8(<8 x i16> %A, <8 x i8> %B) {
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; CHECK-LABEL: vsubws8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubw.s8 q0, q0, d2
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; CHECK-NEXT: bx lr
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%tmp3 = sext <8 x i8> %B to <8 x i16>
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%tmp4 = sub <8 x i16> %A, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vsubws16(<4 x i32> %A, <4 x i16> %B) {
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; CHECK-LABEL: vsubws16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubw.s16 q0, q0, d2
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; CHECK-NEXT: bx lr
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%tmp3 = sext <4 x i16> %B to <4 x i32>
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%tmp4 = sub <4 x i32> %A, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vsubws32(<2 x i64> %A, <2 x i32> %B) {
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; CHECK-LABEL: vsubws32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubw.s32 q0, q0, d2
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; CHECK-NEXT: bx lr
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%tmp3 = sext <2 x i32> %B to <2 x i64>
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%tmp4 = sub <2 x i64> %A, %tmp3
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ret <2 x i64> %tmp4
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}
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define <8 x i16> @vsubwu8(<8 x i16> %A, <8 x i8> %B) {
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; CHECK-LABEL: vsubwu8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubw.u8 q0, q0, d2
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; CHECK-NEXT: bx lr
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%tmp3 = zext <8 x i8> %B to <8 x i16>
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%tmp4 = sub <8 x i16> %A, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vsubwu16(<4 x i32> %A, <4 x i16> %B) {
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; CHECK-LABEL: vsubwu16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubw.u16 q0, q0, d2
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; CHECK-NEXT: bx lr
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%tmp3 = zext <4 x i16> %B to <4 x i32>
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%tmp4 = sub <4 x i32> %A, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vsubwu32(<2 x i64> %A, <2 x i32> %B) {
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; CHECK-LABEL: vsubwu32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubw.u32 q0, q0, d2
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; CHECK-NEXT: bx lr
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%tmp3 = zext <2 x i32> %B to <2 x i64>
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%tmp4 = sub <2 x i64> %A, %tmp3
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ret <2 x i64> %tmp4
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}
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define <8 x i16> @vsubwa8(<8 x i16> %A, <8 x i8> %B) {
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; CHECK-LABEL: vsubwa8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vsubw.u8 q0, q0, d2
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; CHECK-NEXT: vbic.i16 q0, #0xff00
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; CHECK-NEXT: bx lr
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%tmp3 = zext <8 x i8> %B to <8 x i16>
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%tmp4 = sub <8 x i16> %A, %tmp3
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%and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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ret <8 x i16> %and
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}
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define <4 x i32> @vsubwa16(<4 x i32> %A, <4 x i16> %B) {
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; CHECK-LABEL: vsubwa16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q8, #0xffff
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; CHECK-NEXT: vsubw.u16 q9, q0, d2
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; CHECK-NEXT: vand q0, q9, q8
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; CHECK-NEXT: bx lr
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%tmp3 = zext <4 x i16> %B to <4 x i32>
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%tmp4 = sub <4 x i32> %A, %tmp3
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%and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535>
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ret <4 x i32> %and
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}
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define <2 x i64> @vsubwa32(<2 x i64> %A, <2 x i32> %B) {
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; CHECK-LABEL: vsubwa32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i64 q8, #0xffffffff
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; CHECK-NEXT: vsubw.u32 q9, q0, d2
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; CHECK-NEXT: vand q0, q9, q8
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; CHECK-NEXT: bx lr
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%tmp3 = zext <2 x i32> %B to <2 x i64>
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%tmp4 = sub <2 x i64> %A, %tmp3
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%and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295>
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ret <2 x i64> %and
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}
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