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bae3d21c4e
To support OpenCL, which typically uses SPIR as an IR, non-zero address spaces must be accounted for. This patch makes the RISC-V target assume no-op address space casts across the board, which effectively removes the need to support addrspacecast instructions in the backend. For a RISC-V implementation with different configurations or specialized address spaces where casts aren't no-ops, the function can be adjusted as required. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D93536
50 lines
1.5 KiB
LLVM
50 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64I
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define void @cast0(i32 addrspace(1)* %ptr) {
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; RV32I-LABEL: cast0:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sw zero, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: cast0:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sw zero, 0(a0)
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; RV64I-NEXT: ret
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%ptr0 = addrspacecast i32 addrspace(1)* %ptr to i32 addrspace(0)*
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store i32 0, i32* %ptr0
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ret void
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}
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define void @cast1(i32* %ptr) {
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; RV32I-LABEL: cast1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: .cfi_def_cfa_offset 16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: .cfi_offset ra, -4
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; RV32I-NEXT: call foo@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: cast1:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: .cfi_def_cfa_offset 16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: .cfi_offset ra, -8
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; RV64I-NEXT: call foo@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%castptr = addrspacecast i32* %ptr to i32 addrspace(10)*
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call void @foo(i32 addrspace(10)* %castptr)
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ret void
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}
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declare void @foo(i32 addrspace(10)*)
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