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392e36367a
Summary: According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only allow 32-bit instruction alignment, but instruction allow to be aligned to 16-bit boundaries for C-extension. So we just align to 4 bytes and 2 bytes for C-extension is enough. Reviewers: asb, apazos Differential Revision: https://reviews.llvm.org/D45560 Patch by Kito Cheng. llvm-svn: 329899
14 lines
318 B
LLVM
14 lines
318 B
LLVM
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32C
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define void @foo() {
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;RV32I: .p2align 2
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;RV32I: foo:
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;RV32C: .p2align 1
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;RV32C: foo:
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entry:
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ret void
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}
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