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39e5617bc0
Support "Zfh" extension according to https://github.com/riscv/riscv-isa-manual/blob/zfh/src/zfh.tex Differential Revision: https://reviews.llvm.org/D90738
40 lines
1.3 KiB
LLVM
40 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
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; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
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define half @half_imm() nounwind {
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; RV32IZFH-LABEL: half_imm:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: lui a0, %hi(.LCPI0_0)
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; RV32IZFH-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: half_imm:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: lui a0, %hi(.LCPI0_0)
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; RV64IZFH-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
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; RV64IZFH-NEXT: ret
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ret half 3.0
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}
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define half @half_imm_op(half %a) nounwind {
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; RV32IZFH-LABEL: half_imm_op:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
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; RV32IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
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; RV32IZFH-NEXT: fadd.h fa0, fa0, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: half_imm_op:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0)
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; RV64IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
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; RV64IZFH-NEXT: fadd.h fa0, fa0, ft0
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; RV64IZFH-NEXT: ret
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%1 = fadd half %a, 1.0
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ret half %1
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}
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