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95037fa9f6
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
88 lines
2.3 KiB
LLVM
88 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32 %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64 %s
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define void @test1(float* %a, float* %b) nounwind {
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; RV32-LABEL: test1:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: lw a1, 0(a1)
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; RV32-NEXT: lui a2, 524288
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; RV32-NEXT: xor a1, a1, a2
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; RV32-NEXT: sw a1, 0(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test1:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: lw a1, 0(a1)
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; RV64-NEXT: addi a2, zero, 1
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; RV64-NEXT: slli a2, a2, 31
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; RV64-NEXT: xor a1, a1, a2
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; RV64-NEXT: sw a1, 0(a0)
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; RV64-NEXT: ret
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entry:
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%0 = load float, float* %b
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%neg = fneg float %0
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store float %neg, float* %a
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ret void
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}
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define void @test2(double* %a, double* %b) nounwind {
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; RV32-LABEL: test2:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: lw a2, 4(a1)
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; RV32-NEXT: lw a1, 0(a1)
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; RV32-NEXT: lui a3, 524288
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; RV32-NEXT: xor a2, a2, a3
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; RV32-NEXT: sw a1, 0(a0)
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; RV32-NEXT: sw a2, 4(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test2:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: ld a1, 0(a1)
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; RV64-NEXT: addi a2, zero, -1
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; RV64-NEXT: slli a2, a2, 63
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; RV64-NEXT: xor a1, a1, a2
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; RV64-NEXT: sd a1, 0(a0)
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; RV64-NEXT: ret
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entry:
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%0 = load double, double* %b
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%neg = fneg double %0
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store double %neg, double* %a
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ret void
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}
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define void @test3(fp128* %a, fp128* %b) nounwind {
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; RV32-LABEL: test3:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: lw a2, 4(a1)
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; RV32-NEXT: lw a3, 12(a1)
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; RV32-NEXT: lw a4, 8(a1)
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; RV32-NEXT: lw a1, 0(a1)
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; RV32-NEXT: lui a5, 524288
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; RV32-NEXT: xor a3, a3, a5
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; RV32-NEXT: sw a4, 8(a0)
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; RV32-NEXT: sw a1, 0(a0)
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; RV32-NEXT: sw a2, 4(a0)
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; RV32-NEXT: sw a3, 12(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test3:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: ld a2, 8(a1)
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; RV64-NEXT: ld a1, 0(a1)
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; RV64-NEXT: addi a3, zero, -1
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; RV64-NEXT: slli a3, a3, 63
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; RV64-NEXT: xor a2, a2, a3
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; RV64-NEXT: sd a1, 0(a0)
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; RV64-NEXT: sd a2, 8(a0)
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; RV64-NEXT: ret
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entry:
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%0 = load fp128, fp128* %b
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%neg = fneg fp128 %0
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store fp128 %neg, fp128* %a
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ret void
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}
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