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b821e9787f
The previous DAG combiner-based approach had an issue with infinite loops between the target-dependent and target-independent combiner logic (see PR40333). Although this was worked around in rL351806, the combiner-based approach is still potentially brittle and can fail to select the 32-bit shift variant when profitable to do so, as demonstrated in the pr40333.ll test case. This patch instead introduces target-specific SelectionDAG nodes for SHLW/SRLW/SRAW and custom-lowers variable i32 shifts to them. pr40333.ll is a good example of how this approach can improve codegen. This adds DAG combine that does SimplifyDemandedBits on the operands (only lower 32-bits of first operand and lower 5 bits of second operand are read). This seems better than implementing SimplifyDemandedBitsForTargetNode as there is no guarantee that would be called (and it's not for e.g. the anyext return test cases). Also implements ComputeNumSignBitsForTargetNode. There are codegen changes in atomic-rmw.ll and atomic-cmpxchg.ll but the new instruction sequences are semantically equivalent. Differential Revision: https://reviews.llvm.org/D57085 llvm-svn: 352169
21 lines
700 B
LLVM
21 lines
700 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; This test case is significantly simplified from the submitted .ll but
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; demonstrates the same issue. At the time of this problem report, an infinite
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; loop would be created in DAGCombine, converting ANY_EXTEND to SIGN_EXTEND
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; and back again.
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define signext i8 @foo(i32 %a, i32 %b) nounwind {
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; RV64I-LABEL: foo:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srlw a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 56
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; RV64I-NEXT: srai a0, a0, 56
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; RV64I-NEXT: ret
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%1 = lshr i32 %a, %b
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%2 = trunc i32 %1 to i8
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ret i8 %2
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}
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