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llvm-mirror/test
Mikael Holmen ba88ebaa68 [DAG] Don't increase SDNodeOrder for dbg.value/declare.
Summary:
The SDNodeOrder is saved in the IROrder field in the SDNode, and this
field may affects scheduling. Thus, letting dbg.value/declare increase
the order numbers may in turn affect scheduling.

Because of this change we also need to update the code deciding when
dbg values should be output, in ScheduleDAGSDNodes.cpp/ProcessSDDbgValues.

Dbg values now have the same order as the SDNode they are connected to,
not the following orders.

Test cases provided by Florian Hahn.

Reviewers: bogner, aprantl, sunfish, atrick

Reviewed By: atrick

Subscribers: fhahn, probinson, andreadb, llvm-commits, MatzeB

Differential Revision: https://reviews.llvm.org/D25318

llvm-svn: 292485
2017-01-19 13:55:55 +00:00
..
Analysis [SCEV] Make getUDivExactExpr handle non-nuw multiplies correctly. 2017-01-18 23:56:42 +00:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen [DAG] Don't increase SDNodeOrder for dbg.value/declare. 2017-01-19 13:55:55 +00:00
DebugInfo Add -debug-info-for-profiling to emit more debug info for sample pgo profile collection 2017-01-19 00:44:11 +00:00
Examples
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MC AMDGPU: Remove modifiers from v_div_scale_* 2017-01-19 06:04:12 +00:00
Object [Object] Fixup permissions of input files. 2017-01-16 23:28:58 +00:00
ObjectYAML
Other [PM] Add LoopVectorize to the default module pipeline 2017-01-19 02:21:54 +00:00
SymbolRewriter
TableGen
ThinLTO/X86 [ThinLTO] Add a recursive step in Metadata lazy-loading 2017-01-18 18:36:21 +00:00
tools [sancov] applying blacklist to covered points too 2017-01-19 03:49:18 +00:00
Transforms LowerTypeTests: Implement exporting of type identifiers. 2017-01-19 01:20:11 +00:00
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